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EPSON
S1C60N16 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.14 Supply Voltage Detection (SVD) Circuit
4.14.1 Configuration of SVD circuit
The S1C60N16 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find
when the source voltage lowers. The configuration of the SVD circuit is shown in Figure 4.14.1.1.
Turning the SVD operation ON/OFF is controlled through the software (SVDON).
Because the power current consumption of the IC increases when the SVD operation is turned ON, set the
SVD operation to OFF unless otherwise necessary.
VSS
SVD circuit
Data
bus
SVD
sampling
control
VDD
Address 2FFH
SVDON/
SVDDT
Detection output
Fig. 4.14.1.1 Configuration of SVD circuit
In the S1C60N16 Series, the evaluation voltage is set as follows:
S1C60N16: 2.2 V
S1C60L16: 1.2 V
S1C60A16: 2.2 V
See Chapter 7, "Electrical Characteristics", for the evaluation voltage accuracy.
4.14.2 Detection timing of SVD circuit
This section explains the timing for when the SVD circuit writes the result of the supply voltage detection
to the SVD latch.
Turning the SVD operation ON/OFF is controlled through the software (SVDON).
The result of the source voltage detection is written to the SVD latch by the SVD circuit, and this data can
be read out by the software to find the status of the source voltage.
When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection
result is loaded to the SVD latch. To obtain a stable SVD detection result, the SVD circuit must be set to
ON with at least 100 sec. Hence, to obtain the SVD detection result, follow the programming sequence
below.
1. Set SVDON to "1"
2. Maintain at 100 sec minimum
3. Set SVDON to "0"
4. Read out SVDDT
However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N16,
S1C60L16, and S1C60A16, the instruction cycles are long enough, so that there is no need for concern
about maintaining 100 sec for the SVDON = "1" with the software.