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參數(shù)資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 47/105頁 |
| 文件大?。?/td> | 841K |
| 代理商： | S1C60L16F0A0100 |
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36
EPSON
S1C60N16 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7.5 Control of serial interface
The control registers for the serial interface are explained below.
Table 4.7.5.1 Control bits of serial interface
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
5 Undefined
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
2F3H
000
ISIO
R
0 3
ISIO 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (serial I/F)
2E7H
SCTRG
IK10
KCP10
K10
WR
R/W
SCTRG
3
EIK0
KCP10
K10
–
0
– 2
Trigger
Enable
High
–
Mask
Low
Serial I/F clock trigger
Interrupt mask register (K10)
Input comparison register (K10)
Input port data (K10)
2ECH
R13
R12
R11
SIOF
R10
R/W
R
R/W
R13
R12
R11
SIOF
R10
0
High/On
High
Run
High/On
Low/Off
Low
Stop
Low/On
Output port (R13)/BZ output control
Output port (R12)/FOUT output control
Output port (R11)
Output port (SIOF)
Output port (R10)/BZ output control
2F0H
SD3
SD2
SD1
SD0
R/W
SD3
SD2
SD1
SD0
× 5
Serial I/F data register (low-order 4 bits)
2F1H
SD7
SD6
SD5
SD4
R/W
SD7
SD6
SD5
SD4
× 5
Serial I/F data register (high-order 4 bits)
2F2H
SCS1
SCS0
SE2
EISIO
R/W
SCS1
SCS0
SE2
EISIO
1
0
Enable
Mask
Serial I/F clock
mode selection
Serial I/F clock edge selection
Interrupt mask register (serial I/F)
0
CLK
1
CLK/2
2
CLK/4
3
Slave
[SCS1, 0]
Clock
SD0–SD3, SD4–SD7: Serial interface data registers (2F0H, 2F1H)
These registers are used for writing and reading serial data.
During writing operation
When "1" is written : High level
When "0" is written : Low level
Writes serial data will be output to SOUT (P11) terminal. From the SOUT (P11) terminal, the data con-
verted to serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0".
During reading operation
When "1" is read out : High level
When "0" is read out : Low level
The serial data input from the SIN (P10) terminal can be read by this register.
The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from
SIN (P10) terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous
clock is neither being input or output).
At initial reset, these registers will be undefined.
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