參數(shù)資料
型號(hào)： S1C60L16F0A0100
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁數(shù)： 43/105頁
文件大?。?/td> 841K
代理商： S1C60L16F0A0100
32
EPSON
S1C60N16 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7 Serial Interface
4.7.1 Configuration of serial interface
The S1C60N16 Series has a built-in synchronous clock type 8 bits serial interface that can be enabled by
mask option. The configuration of the serial interface is shown in Figure 4.7.1.1.
The CPU, via the 8 bits shift register, can read the serial input data from the SIN (P10) terminal. Moreover,
via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT (P11)
terminal. The synchronous clock for serial data input/output may be set by selecting by software any one
of 3 types of master mode (internal clock mode: when the S1C60N16 Series is to be the master for serial
input/output) and a type of slave mode (external clock mode: when the S1C60N16 Series is to be the
slave for serial input/output).
Furthermore, the R11 output port can be configured to output the SIOF signal, which indicates whether
the serial interface in master or slave mode is ready to transmit/receive or not, by mask option. Also this
option enables the SIOF (2ECHD1) bit that indicates the serial interface operating status.
SD0–SD7
SCS0
SCS1
SE2
Output
latch
EISIO
Serial I/F
interrupt control
circuit
ISIO
SIOF
(R11)
SCTRG
Serial I/F
activating
circuit
System clock
Serial clock
counter
Serial clock
selector
Shift register (8 bits)
Serial clock
generator
SOUT
(P11)
SIN
(P10)
SCLK
(P12)
Fig. 4.7.1.1 Configuration of serial interface
The SIN (P10) and SCLK (P12) terminals have a pull-down resistor. However, the SCLK (P12) terminal is
pulled down to low in external clock mode and the pull-down resistor is disabled in internal clock mode.
4.7.2 Mask option
The serial interface may be selected for the following by mask option.
(1) Whether the serial interface is used or not may be selected. When "use" is selected, the following I/O
port terminals are configured as the serial I/O terminals.
P10
→ SIN (data input)
P11
→ SOUT (data output)
P12
→ SCLK (clock input/output)
(2) Either complementary output or Pch open drain as output specification for the SOUT (P11) terminal
may be selected. However, even if Pch open drain has been selected, application of voltage exceeding
power source voltage to the SOUT (P11) terminal will be prohibited.
(3) As output specification during output mode, either complementary output or Pch open drain output
may be selected for the SCLK (P12) terminal.
(4) Positive or negative logic can be selected for the signal logic of the SIO function. However, keep in
mind that only pull-down resistance can be set for the input mode (pull-up resistance is not built-in).
相關(guān)PDF資料
PDF描述
S1C60N01F 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48
S1C60N02D 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC52
S1C60L02 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60
S1C60N04D 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48
S1C60N08D 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC96
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