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參數(shù)資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 57/105頁 |
| 文件大小： | 841K |
| 代理商： | S1C60L16F0A0100 |
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S1C60N16 TECHNICAL MANUAL
EPSON
45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.8.3 Mask option (segment allocation)
(1) Segment allocation
As shown in Figure 4.1.2, segment data of the S1C60N16 Series is decided depending on display data
written to the display memory at address 040H–065H (Page 0) or 240H–265H (Page 2).
The mask option enables the display memory to be allocated entirely to either Page 0 or Page 2.
The address and bits of the display memory can be made to correspond to the segment terminals
(SEG0–SEG37) in any form through the mask option. This makes design easy by increasing the
degree of freedom with which the liquid crystal panel can be designed.
Figure 4.8.3.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory (when page 0 is selected) for the case of 1/3 duty.
aa'
f
f'
g'
g
ee'
d
d'
p'
p
c'
b'
b
c
SEG10
SEG11
SEG12
Common 0
Common 1
Common 2
09AH
09BH
09CH
09DH
Address
d
p
d'
p'
D3
c
g
c'
g'
D2
b
f
b'
f'
D1
a
e
a'
e'
D0
Data
Display data memory allocation
SEG10
SEG11
SEG12
9A, D0
(a)
9A, D1
(b)
9D, D1
(f')
9B, D1
(f)
9B, D2
(g)
9A, D2
(c)
9B, D0
(e)
9A, D3
(d)
9B, D3
(p)
Pin address allocation
Common 0
Common 1
Common 2
Fig. 4.8.3.1 Segment allocation
(2) Drive duty
According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty.
Table 4.8.3.1 shows the differences in the number of segments according to the selected duty.
Table 4.8.3.1 Differences according to selected duty
Duty
1/4
1/3
1/2
COM used
COM0–COM3
COM0–COM2
COM0–COM1
Max. number of segments
152 (38
× 4)
114 (38
× 3)
76 (38
× 2)
Frame frequency *
fOSC1/1,024 (32 Hz)
fOSC1/768 (42.7 Hz)
fOSC1/1,024 (32 Hz)
When fOSC1 = 32 kHz
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