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參數(shù)資料
| 型號(hào)： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 81/105頁 |
| 文件大?。?/td> | 841K |
| 代理商： | S1C60L16F0A0100 |
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S1C60N16 TECHNICAL MANUAL
EPSON
67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.14.3 Control of SVD circuit
Table 4.14.3.1 shows the SVD circuit's control bits and their addresses.
Table 4.14.3.1 Control bits of SVD circuit
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
5 Undefined
2FFH
SVDDT
SVDON
000
R
W
R
SVDDT
SVDON
0 3
0
– 2
Low
On
–
Normal
Off
–
SVD evaluation data
SVD On/Off
Unused
SVDON/SVDDT: SVD control/SVD data (2FFHD3)
Controls the SVD operation.
When "0" is written : SVD OFF
When "1" is written : SVD ON
When "0" is read out : Supply voltage (VDD–VSS)
≥ 2.2 V (S1C60N16/60A16)/1.2 V (S1C60L16)
When "1" is read out : Supply voltage (VDD–VSS) < 2.2 V (S1C60N16/60A16)/1.2 V (S1C60L16)
Note that the function of this bit when written is different to when read out.
When this bit is written to, ON/OFF of the SVD detection operation is controlled; when this bit is read
out, the result of the SVD detection (contents of SVD latch) is obtained. Appreciable current is consumed
during operation of SVD detection, so keep SVD detection OFF except when necessary.
When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0" the detection
result is loaded to the SVD latch. To obtain a stable detection result, the SVD circuit must be set to ON
with at least 100 sec. Hence, to obtain the detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain at 100 sec minimum
3. Set SVDON to "0"
4. Read out SVDDT
However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N16,
S1C60L16, and S1C60A16, the instruction cycles are long enough, so that there is no need for concern
about maintaining 100 sec for the SVDON = "1" with the software.
4.14.4 Programming notes
(1) The SVD circuit takes 100 sec from the time it goes ON until a stable result is obtained. For this
reason, keep the following software notes in mind:
After writing "1" on SVDON, write "0" after at least 100 sec has elapsed (possible with the next
instruction when the OSC1 clock is used as the CPU clock) and then read the SVDDT.
(2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by
write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth)
cannot be used for SVDON control.
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