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參數(shù)資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 28/105頁 |
| 文件大小： | 841K |
| 代理商： | S1C60L16F0A0100 |
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S1C60N16 TECHNICAL MANUAL
EPSON
19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.5 Control of oscillation circuit (S1C60A16)
Table 4.3.5.1 lists the control bits and their addresses for the oscillation circuit.
Table 4.3.5.1 Control bits of oscillation circuit
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
5 Undefined
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
2FEH
0
CLKCHG OSCC
IOC1
RR/W
0 3
CLKCHG
OSCC
IOC1
– 2
0
–
OSC3
On
Output
–
OSC1
Off
Input
Unused
CPU clock switch
OSC3 oscillation On/Off
I/O control register (P10–P13)
OSCC: OSC3 oscillation control (2FEHD1)
Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C60A16 only.)
When "1" is written : The OSC3 oscillation ON
When "0" is written : The OSC3 oscillation OFF
Read-out : Valid
When it is necessary to operate the CPU of the S1C60A16 at high speed, set OSCC to "1". At other times,
set it to "0" to reduce current consumption.
For S1C60N16 and S1C60L16, keep OSCC set to "0".
At initial reset, OSCC is set to "0".
CLKCHG: CPU clock switch (2FEHD2)
The CPU's operation clock is selected with this register. (S1C60A16 only.)
When "1" is written : OSC3 clock is selected
When "0" is written : OSC1 clock is selected
Read-out : Valid
When the S1C60A16's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This
register cannot be controlled for S1C60N16 and S1C60L16, so that OSC1 is selected no matter what the set
value.
At initial reset, CLKCHG is set to "0".
4.3.6 Programming notes (S1C60A16)
(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
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