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參數(shù)資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 74/105頁 |
| 文件大?。?/td> | 841K |
| 代理商： | S1C60L16F0A0100 |
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60
EPSON
S1C60N16 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
4.12 Event Counter
4.12.1 Configuration of event counter
The S1C60N16 Series has an event counter that counts the clock signals input from outside.
The event counter is configured of a pair of eight-bit binary counters (UP counters). The clock pulses are
input through terminals K02 and K03 of the input port.
The clock signals input from the terminals are input to the event counter via the noise rejector.
The event counter detects the phases of the two clock signals. Software selection provides for two modes,
the phase detection mode in which one of the counters can be chosen to input the clock signal, and the
separate mode in which each clock signal is input to different counters.
Figure 4.12.1.1 shows the configuration of the event counter.
Phase
detection
circuit
Input port
Noise rejector
[EVSEL]
[EVRUN]
K02
K03
Interrupt request
[EV0RST]
[EV1RST]
Event counter 0
[EV00–EV07]
Event counter 1
[EV10–EV17]
[ ] : Register
Noise rejector
Fig. 4.12.1.1 Configuration of event counter
4.12.2 Switching count mode
The event counter detects the phases of the two clock signals. Software selection provides for two modes,
the phase detection mode in which one of the counters can be chosen to input the clock signal, and the
separate mode in which each clock signal is input to different counters.
Selection can be made by writing data to the EVSEL register. When "0" is written the phase detection
mode is enabled, and when "1" is written the separate mode is enabled.
In the phase detection mode, the clock signals having different phases must be input simultaneously to
terminals K02 and K03. When the input from terminal K02 is fast the clock signal is input to event
counter 1, and when the input from terminal K03 is fast the clock signal is input to event counter 0.
In the separate mode, input from terminal K02 is made to event counter 0, and input from terminal K03 is
made to event counter 1.
Figure 4.12.2.1 is the timing chart for the event counter.
相關PDF資料 |
PDF描述 |
|---|---|
| S1C60N01F | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP48 |
| S1C60N02D | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC52 |
| S1C60L02 | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 |
| S1C60N04D | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48 |
| S1C60N08D | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC96 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S1C60N05 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N16 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60R08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63004 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
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