
S1C60N16 TECHNICAL MANUAL
EPSON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(5) LSB first or MSB first as input/output permutation of serial data may be selected in the SIO function.
(6) The output port R11 (see Section 4.5, "Output Ports") can be configured as the SIOF signal output port
to notify the external serial device whether the internal serial interface is ready to transmit/receive
data or not. Also this option switches the function of the R11 output port data bit (2ECHD1) to
indicate the SIOF signal. When this option is selected, the R11 terminal cannot be used as a general-
purpose output port and the R11 port data bit (2ECHD1) cannot be used for setting the output
signal.
4.7.3 Master mode and slave mode of serial interface
The serial interface of the S1C60N16 Series has two types of operation mode: master mode and slave
mode.
In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates
this internal clock at the SCLK (P12) terminal and controls the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address
2F2HD2, D3).
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.7.3.1.
Table 4.7.3.1 Synchronous clock selection
SCS1
0
1
SCS0
0
1
0
1
Mode
Master mode
Slave mode
Synchronous clock
CLK
CLK/2
CLK/4
External clock
CLK: CPU system clock
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as
follows:
At master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically
suspended and SCLK (P12) terminal is fixed at low level.
At slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are masked.
Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous
clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1
fOSC3)
should not be performed.
A sample basic serial input/output portion connection is shown in Figure 4.7.3.1.
S1C60N16
Master mode
Slave mode
SCLK (P12)
SOUT (P11)
SIN (P10)
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C60N16
SCLK (P12)
SOUT (P11)
SIN (P10)
R11(SIOF)
External
serial device
CLK
SOUT
SIN
Input terminal
Fig. 4.7.3.1 Sample basic connection