
11 16-bit Timer (T16)
11-10
EPSON
S1C17003 TECHNICAL MANUAL
11.8 16-bit Timer Interrupts
The 16-bit timer outputs interrupt requests to the interrupt controller (ITC) when the counter underflows.
Underflow interrupt
Generated by a counter underflow, this interrupt request sets the interrupt flag T16IF (D0/T16_INTx register)
to 1 inside the T16 module provided for each channel.
T16IF: 16-bit Timer Interrupt Flag in the 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register
(D0/0x4228/0x4248/0x4268)
To use this interrupt, set T16IE (D8/T16_INTx register) to 1. If T16IE is set to 0 (default), T16IF will not be set
to 1, and the interrupt request for this cause will not be sent to the ITC.
T16IE: 16-bit Timer Interrupt Enable Bit in the 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register
(D8/0x4228/0x4248/0x4268)
If T16IF is set to 1, the T16 module outputs an interrupt request to the ITC. An interrupt is generated if
interrupt conditions are satisfied for the ITC and S1C17 core.
Note: The T16 module interrupt flag T16IF must be reset within the interrupt processing routine
following a 16-bit timer interrupt to prevent recurring interrupts.
Reset T16IF before permitting 16-bit timer interrupts with T16IE to prevent unwanted
interrupts occurring.
Interrupt vectors
The timer interrupt vector numbers and vector addresses are listed below.
Table 11.8.1: Timer interrupt vectors
Timer channel
Vector number
Vector address
16-bit Timer Ch.0
13 (0x0d)
TTBR + 0x34
16-bit Timer Ch.1
14 (0x0e)
TTBR + 0x38
16-bit Timer Ch.2
15 (0x0f)
TTBR + 0x3c
Other interrupt settings
The ITC allows the precedence of 16-bit timer interrupts to be set between level 0 (default) and level 7 for each
channel. The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1 to
generate actual interrupts.
For specific information on interrupt processing, see “6 Interrupt Controller (ITC).”