
7 Oscillator Circuit (OSC)
7-6
EPSON
S1C17003 TECHNICAL MANUAL
7.6 Clock External Output (FOUTH, FOUT1)
The HSCLKdivision clock (FOUTH) and OSC1 clock (FOUT1) can be output to devices outside the chip.
Division circuit
(1/1 to 1/4)
FOUTH(P40)
HSCLK clock
FOUTH
Output circuit
P40 port
On/off control
P40 function selection
P35 function selection
Division ratio selection
FOUT1(P35)
OSC1 clock
FOUT1
Output circuit
P35 port
On/off control
Figure 7.6.1: Clock output circuit
FOUTH output
FOUTH is the HSCLK division clock.
Output pin setting
The FOUTH output pin is combined with the P40 port. This functions as the P40 port pin by default, so
the pin function should be changed by writing 1 to P40MUX (D0/P4_PMUX register) if use is required for
FOUTH output.
P40MUX: P40 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D0/0x52a8)
FOUTH clock frequency selection
Three different clock output frequencies can be selected. Select the division ratio for the OSC3 clock using
FOUTHD[1:0] (D[3:2]/OSC_FOUT register).
FOUTHD[1:0]:FOUTH Clock Division Ratio Select Bits in the FOUT Control (OSC_FOUT) Register
(D[3:2]/0x5064)
Table 7.6.1: FOUTH clock division ratio selection
FOUTHD[1:0]
Division ratio
0x3
Reserved
0x2
OSC3-1/4
0x1
OSC3-1/2
0x0
OSC3-1/1
(Default: 0x0)
Clock output control
The clock output is controlled using the FOUTHE (D1/OSC_FOUT register). Setting FOUTHE to 1 outputs
the FOUTH clock from the FOUTH pin. Setting it to 0 halts output.
FOUTHE: FOUTH Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064)
FOUT3E
FOUTH output (P30)
0
1
Figure 7.6.2: FOUTH output
Notes: Since the FOUTH signal is asynchronized with FOUTHE writing, switching output on or off will
generate certain hazards.
Change of the single selection (FOUTHD [1:0] (D[3:2]/0x5064) of FOUTH clock frequency
should be executed when FOUTHE (D1/0x5064) is 0 and clock output is in “Stop” status.