
14 8-bit OSC1 Timer (T8OSC1)
S1C17003 TECHNICAL MANUAL
EPSON
14-7
T8OSC1
14.7 8-bit OSC1 Timer Interrupts
The T8OSC1 module outputs an interrupt request to the interrupt controller (ITC) by compare match.
Compare match interrupt
This interrupt request is generated when the counter matches the compare data register setting during counting.
It sets the interrupt flag T8OIF (D0/T8OSC1_IFLG register) within the T8OSC1 module to 1.
 T8OIF: 8-bit OSC1 Timer Interrupt Flag in the 8-bit OSC1 Timer Interrupt Flag (T8OSC1_IFLG) Register
(D0/0x50c4)
To use this interrupt, set T8OIE (D0/T8OSC1_IMSK register) to 1. If T8OIE is set to 0 (default), T8OIE is not
set to 1, and the interrupt request for this factor is not sent to the ITC.
 T8OIE: 8-bit OSC1 Timer Interrupt Enable Bit in the 8-bit OSC1 Timer Interrupt Mask (T8OSC1_IMSK)
Register (D0/0x50c3)
If T8OIF is set to 1, the T8OSC1 module outputs an interrupt request to the ITC. This interrupt request signal
generates an interrupt if the ITC and S1C17 core interrupt conditions are satisfied.
Note:  To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF must be reset
within the interrupt handler routine following an 8-bit OSC1 timer interrupt.
 To prevent generating unnecessary interrupts, reset the corresponding T8OIF before
permitting compare 8-bit OSC1 interrupts from T8OIE.
Interrupt vectors
The 8-bit OSC timer interrupt vector numbers and vector addresses are listed below.
Vector number: 8 (0x08)
Vector address: TTBR + 0x20
Other interrupt settings
The ITC allows the priority of 8-bit OSC1 timer interrupts to be set between level 0 (the default value) and level 7.
To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit
must be set to 1.
For more information on interrupt processing, see “6 Interrupt Controller (ITC).”