
22 Remote Controller (REMC)
S1C17003 TECHNICAL MANUAL
EPSON
22-5
22.5 Data Transfer Control
Make the following settings before starting data transfers.
(1) Set the carrier signal. (See Section 22.3.)
(2) Select the data length counter clock. (See Section 22.4.)
(3) Set the interrupt conditions. (See Section 22.6.)
Note: Make sure the REMC module is halted (when REMEN/REMC_CFG register = 0) before
changing the above settings.
REMEN: REMC Enable Bit in the REMC Configuration (REMC_CFG) Register (D0/0x5340)
Data transfer control
REMDT
REMO pin output
Carrier
REMDT
REMO pin output
Figure 22.5.1: Data transmission
PCLK
PSC output clock
(data length counter clock)
REMLEN[7:0]
Interrupt signal
4
3
2
1
0
Figure 22.5.2: Underflow interrupt generation timing
(1) Data transmit mode setting
Set REMC to transmit mode by writing 0 to REMMD (D1/REMC_CFG register).
REMMD: REMC Mode Select Bit in the REMC Configuration (REMC_CFG) Register (D1/0x5340)
(2) Permit data transmission
Permit REMC operation by setting REMEN (D0/REMC_CFG register) to 1. This initiates REMC transmission.
Set REMDT (D0/REMC_ST register) to 0 and REMLEN[7:0] (D[7:0]/REMC_LCNT register) to 0x0 before
setting REMEN to 1 to prevent unnecessary data transmission.
(3) Transmission data settings
Set the data to be transmitted (High or Low) to REMDT (D0/REMC_ST register).
REMDT: Transmit/Receive Data Bit in the REMC Status (REMC_ST) Register (D0/0x5344)
Setting REMDT to 1 outputs High; setting it to 0 outputs Low from the REMO pin after being modulated by
the carrier signal.
(4) Data pulse length setting
Set the value corresponding to the data pulse length (High or Low section) at the start of transmission to
REMLEN[7:0] (D[15:8]/REMC_LCNT register) to set to the data length counter.
REMLEN[7:0]: Transmit/Receive Data Length Count Bits in the REMC Length Counter (REMC_LCNT)
Register (D[15:8]/0x5344)
REMC