
10 Input/Output Port (P)
10-8
EPSON
S1C17003 TECHNICAL MANUAL
Interrupt flags
The ITC is able to accept interrupt requests for both P0 and P1 port interrupts, and the P port module contains
interrupt flags PxIF[7:0] corresponding to the individual 16 ports to enable individual control of the 16 P0[7:0]
and P1[7:0] port interrupts. PxIF[7:0] will be set to 1 at the specified edge (rising or falling edge) of the input
signal. A P0 or P1 port interrupt request signal is also output to the ITC at the same time if the corresponding
PxIE[7:0] is set to 1. Meeting the ITC and S1C17 core interrupt conditions generates an interrupt.
P0IF[7:0]: P0[7:0] Port Interrupt Flags in the P0 Port Interrupt Flag (P0_IFLG) Register (D[7:0]/0x5207)
P1IF[7:0]: P1[7:0] Port Interrupt Flags in the P1 Port Interrupt Flag (P1_IFLG) Register (D[7:0]/0x5217)
PxIF[7:0] is reset by writing as 1.
Note: The P port module interrupt flag PxIF[7:0] must be reset within the interrupt processing
routine following a port interrupt to prevent recurring interrupts.
To prevent generating unnecessary interrupts, reset the relevant PxIF[7:0] before permitting
interrupts for the required port using PxIE[7:0] (Px_IMSK register).
Interrupt vector
The port interrupt vector numbers and vector addresses are as shown below.
Table 10.6.1: Port interrupt vectors
Port
Vector number
Vector address
P0
4 (0x04)
TTBR + 0x10
P1
5 (0x05)
TTBR + 0x14
Other interrupt settings
The ITC allows the precedence of P0 and P1 port interrupts to be set between level 0 (default) and level 7. The
PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1 to generate actual
interrupts.
For specific information on interrupt processing, see “6 Interrupt Controller (ITC).”