
22 Remote Controller (REMC)
S1C17003 TECHNICAL MANUAL
EPSON
22-11
0x5340: REMC Configuration Register (REMC_CFG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
REMC
Configuration
Register
(REMC_CFG)
0x5340
(16 bits)
D15–12 CGCLK[3:0] Carrier generator clock select
(Prescaler output clock)
CGCLK[3:0]
LCCLK[3:0]
Clock
0x0 R/W
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
D11–8 LCCLK[3:0] Length counter clock select
(Prescaler output clock)
0x0 R/W
D7–2 –
reserved
–
0 when being read.
D1
REMMD
REMC mode select
1 Receive
0 Transmit
0
R/W
D0
REMEN
REMC enable
1 Enable
0 Disable
0
R/W
D[15:12] CGCLK[3:0]: Carrier Generator Clock Select Bits
Select a carrier generation clock from the 15 prescaler output clocks.
Table 22.7.2: Carrier generation clock selection
CGCLK[3:0]
Prescaler output clock
CGCLK[3:0]
Prescaler output clock
0xf
Reserved
0x7
PCLK-1/128
0xe
PCLK-1/16384
0x6
PCLK-1/64
0xd
PCLK-1/8192
0x5
PCLK-1/32
0xc
PCLK-1/4096
0x4
PCLK-1/16
0xb
PCLK-1/2048
0x3
PCLK-1/8
0xa
PCLK-1/1024
0x2
PCLK-1/4
0x9
PCLK-1/512
0x1
PCLK-1/2
0x8
PCLK-1/256
0x0
PCLK-1/1
(Default: 0x0)
D[11:8]
LCCLK[3:0]: Length Counter Clock Select Bits
Select a data length counter clock from the 15 prescaler output clocks.
Table 22.7.3: Carrier generation clock selection
LCCLK[3:0]
Prescaler output clock
LCCLK[3:0]
Prescaler output clock
0xf
Reserved
0x7
PCLK-1/128
0xe
PCLK-1/16384
0x6
PCLK-1/64
0xd
PCLK-1/8192
0x5
PCLK-1/32
0xc
PCLK-1/4096
0x4
PCLK-1/16
0xb
PCLK-1/2048
0x3
PCLK-1/8
0xa
PCLK-1/1024
0x2
PCLK-1/4
0x9
PCLK-1/512
0x1
PCLK-1/2
0x8
PCLK-1/256
0x0
PCLK-1/1
(Default: 0x0)
Note: The clock should be set only while the REMC module is stopped (REMEN(D0) = 0).
D[7:2]
Reserved
D1
REMMD: REMC Mode Select Bit
Selects the transfer direction.
1 (R/W): Receive
0 (R/W): Transmit (default)
REMC