
25 Multiplier/Divider
25-4
EPSON
S1C17003 TECHNICAL MANUAL
25.4 Division
The division function executes "A (16 bits) = B (16 bits) ÷ C (16 bits), D (16 bits) = Remainder."
To perform a division, set the operating mode to 0x8 (unsigned division) or 0x9 (signed division). Next, transfer the
16-bit dividend (B) and 16-bit divisor (C) to the multiplier/divider using the "1d.ca" instruction. The quotient will
be placed in the lower 16 bits of the arithmetic result register, while the remainder is placed in the upper 16 bits.
When the calculation is completed, the 16 bits corresponding to the quotient or remainder as specified in the output
mode and the flag status are returned to the CPU register. The other 16 bits of the arithmetic result can be read out
by setting the multiplier/divider to arithmetic result reading mode.
S1C17 core
Arithmetic result
register
Selector
Argument 2
Argument 1
16 bits
÷
16 bits
Coprocessor
output (16 bits)
Flag output
Arithmetic
result
Figure 25.4.1 Division mode data path
Table 25.4.1 Division mode operations
Mode
setting
Instruction
Operation
Flag
Remarks
0x08
or
0x09
ld.ca %rd,%rs
res[31:0]
← %rd ÷ %rs
%rd
← res[15:0] (quotient)
psr (CVZN)
← 0b0000 The arithmetic result register re-
tains the calculated result until
it is overwritten by the result of
another arithmetic operation.
(ext
imm9)
ld.ca %rd,imm7
res[31:0]
← %rd ÷ imm7/16
%rd
← res[15:0] (quotient)
0x18
or
0x19
ld.ca %rd,%rs
res[31:0]
← %rd ÷ %rs
%rd
← res[31:16]
(remainder)
(ext
imm9)
ld.ca %rd,imm7
res[31:0]
← %rd ÷
imm7/16 %rd
← res[31:16]
(remainder)
res: Arithmetic result register
Example:
ld.cw %r0,0x8
; Mode setting (unsigned division mode & lower 16-bit output mode)
ld.ca %r0,%r1
; Executes "res = %r0 + %r1" and loads the lower 16 bits (quotient) of the result to the
%r0 register.
ld.cw %r0,0x13 ; Mode setting (arithmetic result reading mode & upper 16-bit output mode)
ld.ca %r1,%r0
; Loads the upper 16 bits (remainder) of the result to the %r1 register.