
22 Remote Controller (REMC)
S1C17003 TECHNICAL MANUAL
EPSON
22-9
Falling edge interrupt
Generated when the REMI pin input signal changes from High to Low, this interrupt request sets the interrupt
flag REMRIF (D2/REMC_INT register) to 1 within the REMC.
When data is being received, the data length counter can be operated between this interrupt and a falling edge
interrupt to calculate the received data pulse width from that count value.
REMFIF: Falling Edge Interrupt Flag in the REMC Interrupt Flag (REMC_INT) Register (D2/0x5346)
To use this interrupt, set REMFIE (D2/REMC_IMSK register) to 1. If REMFIE is set to 0 (default), REMFIF is
not set to 1 and the interrupt request for this factor is not sent to the ITC.
REMFIE: Falling Edge Interrupt Enable Bit in the REMC Interrupt Mask (REMC_INT) Register (D2/0x5346)
When REMFIF is set to 1, REMC outputs an interrupt request to the ITC. This interrupt request signal sets the
REMC interrupt flag to 1 within the ITC, generating an interrupt if the ITC and S1C17 core interrupt conditions
are met.
REMFIF should be inspected as part of the REMC interrupt processing routine to determine whether the
REMC interrupt is attributable to input signal falling edge.
The interrupt factor should be cleared as part of the interrupt processing routine by resetting both the ITC
REMC interrupt flag and REMC module REMFIF (i.e., setting both to 1).
Interrupt vectors
The REMC interrupt vector numbers and vector addresses are as listed below.
Vector number: 20 (0x14)
Vector address: TTBR + 0x50
Other interrupt settings
The ITC allows the priority of REMC interrupts to be set between level 0 (the default value) and level 7. To
generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must
be set to 1.
For more information on interrupt processing, see “6 Interrupt Controller (ITC).”
REMC