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參數(shù)資料
| 型號(hào)： | PSD854F2A-90MT |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 95/128頁(yè) |
| 文件大?。?/td> | 1045K |
| 代理商： | PSD854F2A-90MT |
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PSD8XXFX
I/O ports
Doc ID 7833 Rev 7
16.3
MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD are mapped into the MCU address
space. The addresses of the ports are listed in Table 8.
A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the
Control register. The MCU I/O direction may be changed by writing to the corresponding bit
in the Direction register, or by the output enable product term (see Section 16.8: Peripheral
I/O mode). When the pin is configured as an output, the content of the Data Out register
drives the pin. When configured as an input, the MCU can read the port input through the
Data In buffer (see Figure 25).
Ports C and D do not have Control registers, and are in MCU I/O mode by default. They can
be used for PLD I/O if equations are written for them in PSDabel.
16.4
PLD I/O mode
The PLD I/O mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as
an output from the CPLD’s Output macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction register to ’0.’ The corresponding
bit in the Direction register must not be set to '1' if the pin is defined for a PLD input signal in
PSDabel. The PLD I/O mode is specified in PSDabel by declaring the port pins, and then
writing an equation assigning the PLD I/O to a port.
16.5
Address Out mode
For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive
latched addresses on to the port pins. These port pins can, in turn, drive external devices.
Either the output enable or the corresponding bits of both the Direction register and Control
register must be set to a 1 for pins to use Address Out mode. This must be done by the
MCU at run-time. See Table 22 for the address output pin assignments on ports A and B for
various MCUs.
For non-multiplexed 8-bit bus mode, address signals (A7-A0) are available to port B in
Address Out mode.
Note:
Do not drive address signals with Address Out mode to an external memory device if it is
intended for the MCU to Boot from the external device. The MCU must first Boot from PSD
memory so the Direction and Control register bits can be set.
Table 20.
Port operating modes
Port mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
PLD I/O
McellAB outputs
McellBC outputs
Additional Ext. CS outputs
PLD inputs
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD854F2A-90UT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| PSH665-FREQ-OUT1 | VCXO, SINE OUTPUT, 465 MHz - 865 MHz |
| PSM3-022K | 1 ELEMENT, 0.022 uH, GENERAL PURPOSE INDUCTOR, SMD |
| PSM3-068K | 1 ELEMENT, 0.068 uH, GENERAL PURPOSE INDUCTOR, SMD |
| PSM3-120K | 1 ELEMENT, 0.12 uH, GENERAL PURPOSE INDUCTOR, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD854F2V-12JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-12MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90M | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD-8M-01 | 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC |
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