參數(shù)資料
型號： PSD854F2A-90MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù)： 108/128頁
文件大小： 1045K
代理商： PSD854F2A-90MT
Power management
PSD8XXFX
Doc ID 7833 Rev 7
17.1
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes high, and the PSD enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operating mode. The PSD also returns to normal operating mode if either PSD Chip
Select input (CSI, PD2) is low or the Reset (RESET) input is high.
●
The MCU address/data bus is blocked from all memory and PLDs.
●
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from
the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All PSD memories enter Standby mode and are drawing standby current. However, the
PLD and I/O ports blocks do not go into Standby mode because you don’t want to have
to wait for the logic and I/O to “wake up” before their outputs can change. See Table 29
for Power-down mode effects on PSD ports.
●
Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
Table 29.
Power-down mode’s effect on ports
Port function
Pin level
MCU I/O
No change
PLD Out
No change
Address Out
Undefined
Data port
Tri-state
Peripheral I/O
Tri-state
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PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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