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參數(shù)資料
| 型號： | PSD854F2A-90MT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFP-52 |
| 文件頁數(shù)： | 57/128頁 |
| 文件大?。?/td> | 1045K |
| 代理商： | PSD854F2A-90MT |
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Programming Flash memory
PSD8XXFX
Doc ID 7833 Rev 7
8
Programming Flash memory
Flash memory must be erased prior to being programmed. A byte of Flash memory is
erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may
erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may
program Flash memory byte-by-byte.
The primary and secondary Flash memories require the MCU to send an instruction to
program a byte or to erase sectors (see Table 10).
Once the MCU issues a Flash memory Program or Erase instruction, it must check for the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or Ready/Busy (PC3).
8.1
Data Polling
Polling on the Data Polling flag bit (DQ7) is a method of checking whether a program or
erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the byte to be programmed in Flash memory to
check status. The Data Polling flag bit (DQ7) of this location becomes the complement of b7
of the original data byte to be programmed. The MCU continues to poll this location,
comparing the Data Polling flag bit (DQ7) and monitoring the Error flag bit (DQ5). When the
Data Polling flag bit (DQ7) matches b7 of the original data, and the Error flag bit (DQ5)
remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU
should test the Data Polling flag bit (DQ7) again since the Data Polling flag bit (DQ7) may
have changed simultaneously with the Error flag bit (DQ5, see Figure 6).
The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method during an Erase cycle, Figure 6 still applies. However,
the Data Polling flag bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error flag bit
(DQ5) indicates a timeout condition on the Erase cycle; a 0 indicates no error. The MCU can
read any location within the sector being erased to get the Data Polling flag bit (DQ7) and
the Error flag bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Polling
algorithms.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD854F2V-12JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-12MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90M | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD-8M-01 | 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC |
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