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| 型號(hào)： | PSD854F2A-90MT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 79/128頁(yè) |
| 文件大?。?/td> | 1045K |
| 代理商： | PSD854F2A-90MT |
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PLDS
PSD8XXFX
Doc ID 7833 Rev 7
14.5
Product Term Allocator
The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term
Allocator to borrow and place product terms from one macrocell to another. The following list
summarizes how product terms are allocated:
●
McellAB0-McellAB7 all have three native product terms and may borrow up to six more
●
McellBC0-McellBC3 all have four native product terms and may borrow up to five more
●
McellBC4-McellBC7 all have four native product terms and may borrow up to six more.
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required, which consume other Output macrocells (OMC). If external product
terms are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft Express performs this expansion as needed.
14.6
Loading and reading the Output macrocells (OMC)
The Output macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP block (see Section 16: I/O ports). The flip-flops in each of
the 16 Output macrocells (OMC) can be loaded from the data bus by a MCU. Loading the
Output macrocells (OMC) with data from the MCU takes priority over internal functions. As
such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is useful in such applications as loadable
counters and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the Output macrocells (OMC) on the trailing edge of Write Strobe
(WR, CNTL0) (edge loading) or during the time that Write Strobe (WR, CNTL0) is active
(level loading). The method of loading is specified in PSDsoft Express Configuration.
14.7
The OMC Mask register
There is one Mask register for each of the two groups of eight Output macrocells (OMC).
The Mask registers can be used to block the loading of data to individual Output macrocells
(OMC). The default value for the Mask registers is 00h, which allows loading of the Output
macrocells (OMC). When a given bit in a Mask register is set to a 1, the MCU is blocked
from writing to the associated Output macrocells (OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You would not want a MCU write to McellAB
to overwrite the state machine registers. Therefore, you would want to load the Mask
register for McellAB (Mask macrocell AB) with the value 0Fh.
14.8
The Output Enable of the OMC
The Output macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
AND Array, ORed with the Direction register output. The pin is enabled upon Power-up if no
output enable equation is defined and if the pin is declared as a PLD output in PSDsoft
Express.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD854F2A-90UT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| PSH665-FREQ-OUT1 | VCXO, SINE OUTPUT, 465 MHz - 865 MHz |
| PSM3-022K | 1 ELEMENT, 0.022 uH, GENERAL PURPOSE INDUCTOR, SMD |
| PSM3-068K | 1 ELEMENT, 0.068 uH, GENERAL PURPOSE INDUCTOR, SMD |
| PSM3-120K | 1 ELEMENT, 0.12 uH, GENERAL PURPOSE INDUCTOR, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD854F2V-12JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-12MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90M | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD-8M-01 | 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC |
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