參數(shù)資料
型號： PSD854F2A-90MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù)： 50/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90MT
Detailed operation
PSD8XXFX
Doc ID 7833 Rev 7
Table 10.
Instructions (1)(2)(3)
Instruction
FS0-FS7 or
CSBOOT0-
CSBOOT3
(4)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
READ(5)
1
“READ”
RD @ RA
Read Main
Flash ID(6)
1
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read identifier
(A6,A1,A0 = 0,0,1)
Read Sector
Protection(6)(7)
(8)
1
AAh@
X555h
55h@
XAAAh
90h@
X555h
Read identifier
(A6,A1,A0 = 0,1,0)
Program a
Flash Byte(8)
1
AAh@
X555h
55h@
XAAAh
A0h@
X555h
PD@ PA
Flash Sector
Erase(9)(8)
1
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@ X555h
55h@
XAAAh
30h@
SA
30h7@
next SA
Flash Bulk
1
AAh@
X555h
55h@
XAAAh
80h@
X555h
AAh@ X555h
55h@
XAAAh
10h@
X555h
Suspend
Sector
Erase(10)
1
B0h@
XXXXh
Resume
Sector
Erase(11)
1
30h@
XXXXh
Reset(6)
1
F0h@
XXXXh
Unlock Bypass
1
AAh@
X555h
55h@
XAAAh
20h@
X555h
Unlock Bypass
Program(12)
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset(13)
1
90h@
XXXXh
00h@
XXXXh
1.
All bus cycles are WRITE bus cycles, except the ones with the “READ” label
2.
All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR,
CNTL0). PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to
be erased, or verified, must be Active (high).
3.
Only address bits A11-A0 are used in instruction decoding.
4.
Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express.
5.
No Unlock or instruction cycles are required when the device is in the READ mode
6.
The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector
Protection Status, or if the Error flag bit (DQ5/DQ13) goes high.
7.
The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
and (A1,A0)=(1,0)
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PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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