參數(shù)資料
型號(hào)： PSD854F2A-90MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù)： 101/128頁
文件大小： 1045K
代理商： PSD854F2A-90MT
I/O ports
PSD8XXFX
Doc ID 7833 Rev 7
16.14
Port Data registers
The port Data registers, shown in Table 28, are used by the MCU to write data to or read
data from the ports. Table 28 shows the register name, the ports having each register type,
and MCU access for each register type. The registers are described below.
16.15
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is
read through the Data In buffer.
16.16
Data Out register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
register are driven out to the pins if the Direction register or the output enable product term
is set to ’1.’ The contents of the register can also be read back by the MCU.
Output macrocells (OMC)
The CPLD Output macrocells (OMC) occupy a location in the MCU’s address space. The
MCU can read the output of the Output macrocells (OMC). If the OMC Mask register bits are
not set, writing to the macrocell loads data to the macrocell flip-flops (see Section 14:
16.17
OMC Mask register
Each OMC Mask register bit corresponds to an Output macrocell (OMC) flip-flop. When the
OMC Mask register bit is set to a 1, loading data into the Output macrocell (OMC) flip-flop is
blocked. The default value is 0 or unblocked.
16.18
Input macro (IMC)
The input macrocells (IMC) can be used to latch or store external inputs. The outputs of the
input macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU (see
Table 28.
Port Data registers
Register name
Port
MCU access
Data In
A,B,C,D
READ – input on pin
Data Out
A,B,C,D
WRITE/READ
Output macrocell
A,B,C
READ – outputs of macrocells
WRITE – loading macrocells flip-flop
Mask macrocell
A,B,C
WRITE/READ – prevents loading into a given
macrocell
Input macrocell
A,B,C
READ – outputs of the input macrocells
Enable Out
A,B,C
READ – the output enable control of the port driver
相關(guān)PDF資料
PDF描述
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
PSH665-FREQ-OUT1 VCXO, SINE OUTPUT, 465 MHz - 865 MHz
PSM3-022K 1 ELEMENT, 0.022 uH, GENERAL PURPOSE INDUCTOR, SMD
PSM3-068K 1 ELEMENT, 0.068 uH, GENERAL PURPOSE INDUCTOR, SMD
PSM3-120K 1 ELEMENT, 0.12 uH, GENERAL PURPOSE INDUCTOR, SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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