參數(shù)資料
型號(hào): PSD854F2A-90MT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: ROHS COMPLIANT, PLASTIC, QFP-52
文件頁(yè)數(shù): 36/128頁(yè)
文件大?。?/td> 1045K
代理商: PSD854F2A-90MT
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PSD8XXFX
Pin description
Doc ID 7833 Rev 7
2
Pin description
Table 3.
PLCC52 pin description (1)
Pin name
Pin
Description
ADIO0-7
30-37
I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.
If your MCU does not have a multiplexed address/data bus, or you are using an 80C251
in page mode, connect A0-A7 to this port.
If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this port
are passed to the PLDs.
ADIO8-15
39-46
I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.
If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port.
If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this port
are passed to the PLDs.
CNTL0
47
I
The following control signals can be connected to this port, based on your MCU:
WR – active low Write Strobe input.
R_W – active high READ/active low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
CNTL1
50
I
The following control signals can be connected to this port, based on your MCU:
RD – active low Read Strobe input.
E – E clock input.
DS – active low Data Strobe input.
PSEN – connect PSEN to this port when it is being used as an active low READ signal.
For example, when the 80C251 outputs more than 16 address bits, PSEN is actually
the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
CNTL2
49
I
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.
Reset
48
I
Resets I/O ports, PLD macrocells and some of the Configuration registers. Must be low
at Power-up.
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PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC