參數(shù)資料
型號： PSD854F2A-90MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù)： 109/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90MT
PSD8XXFX
Power management
Doc ID 7833 Rev 7
Figure 31.
APD unit
17.2
For users of the HC11 (or compatible)
The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or
compatible) in your design, and you wish to use the Power-down mode, you must not
connect the E clock to CLKIN (PD1). You should instead connect a crystal oscillator to
CLKIN (PD1). The crystal oscillator frequency must be less than 15 times the frequency of
AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS,
the PSD keeps going into Power-down mode.
17.3
Other power saving options
The PSD offers other reduced power saving options that are independent of the Power-
down mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
SELECT
AI02891
Table 30.
PSD timing and standby current during Power-down mode
Mode
PLD propagation delay
Memory
access time
Access recovery time
to normal access
Typical standby current
5V VCC
3V VCC
Power-down
Normal tPD
(1)
No access
tLVDV
75 A(2)
25 A(2)
1.
Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2.
Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
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