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參數(shù)資料
| 型號(hào)： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶(hù)手冊(cè) |
| 文件頁(yè)數(shù)： | 64/186頁(yè) |
| 文件大小： | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
52
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
DTR (I) - Data Terminal Ready. This signal is used by the software on the PQ2FADS-VR to
detect if a terminal is connected to the board.
DSR (O) - Data Set Ready. This line is always asserted by the PQ2FADS-VR.
RTS (I) - Request To Send. This line is not connected in the PQ2FADS-VR.
CTS (O) - Clear To Send. This line is always asserted by the PQ2FADS-VR.
NOTE:
RS232 port 2 (SCC2) functionality is in conflict with ATM 16 bit UTOPIA bus
and Multi PHY UTOPIA bus. RS232 port 1 is in conflict with Multi PHY
UTOPIA bus. It is up to the user to determine the desired function on the shared
pins.
4.12.4 USB Port
The USB port resides on the PQ2FADS-VR and is driven by the USB port of the MPC8275 (Hip7
only) through SCC4. A dedicated USB transceiver - the PDIUSBP11 by PHILIPS is provided,
along with a tri-state buffer, separating this port from the MPC8275’s USB port, this to allow Port
disable option and off-board use of MPC8275 USB pins.
To correctly support the 2 speed modes of the USB, detachable pull-up resistors (3.3V) are
provided over D+ and D- lines of the USB, controlled by the USB_SPD bit of BCSR4. When
USB_SPD is in low-speed level (low) D- is pulled-up while D+ remains floating. When
USB_SPD bit is in high-speed level, D+ is being pulled-up and D- floats.
Also, 5V power will optionally be provided for the USB connector, controlled by USB_VCC0 in
BCSR4. When USB_VCC0 is driven low, a 5V supply will be connected to pin 1 of the USB
connectors.
NOTE:
The USB function is in conflict with ATM 16 bit UTOPIA bus and Fast Ethernet
MDC functions. It is up to the user to select the desired function on the shared
pins.
4.12.5 PC Parallel Port
A new feature to this board is the direct connection to a PC parallel port for the purpose of
debugger connection (CodeWarrior). An on-board logic is used to interface to the parallel port
and translate the signals to COP/JTAG format. The parallel port support both EPP and SPP modes
of the parallel port in a PC. The direct connection eliminates the need for an external command
converter. When connected to a PC’s parallel port, the parallel port connection has automatic
priority over the COP/JTAG connector interface.
4.13
Board Control & Status Register - BCSR
Most of the hardware options on the PQ2FADS-VR are controlled or monitored by the BCSR,
which is a 32 bit wide read / write register file. The BCSR is accessed via the PQ2s’ memory
controller (see
Table 4-5.
) and in fact includes 8 registers: BCSR0 to BCSR7. Since the minimum
block size for a CS region is 32KBytes and only A(27:29) lines are decoded by the BCSR for
F
Freescale Semiconductor, Inc.
n
.
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