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| 型號(hào)： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶手冊(cè) |
| 文件頁數(shù)： | 38/186頁 |
| 文件大?。?/td> | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
26
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
4.1.2.3 Internal Sources Hard - Reset
The PQ2 has internal sources which generate Hard Reset. Among these sources are:
1. Loss of Lock Reset. When one of the PLLs (Core, CPM), is out of lock, hard-reset is gen-
erated.
2. Check-Stop Reset. When the core enters a Check-Stop state from some reason, hard-reset
may be generated, depended on CSRE bit in the RMR.
3. Bus Monitor Reset. When the bus monitor is enabled and a bus cycle is not terminated,
hard-reset is generated.
4. S/W Watch Dog Reset. When the S/W watch-dog is enabled, and application s/w fails to
perform its reset routine, it will generate hard - reset.
5. COP/JTAG Reset (Internal). Hard reset may be forced by driving the HRESET line via the
external pin’s scan chain. Not useful for run time.
In general, the PQ2 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset
source has been identified. A hard reset sequence is followed by a soft reset sequence.
4.1.2.4 Hard Reset Configuration
When Hard-Reset is applied to the PQ2 (externally as well as internally), it samples the Hard-
Reset configuration word. This configuration may be taken from an internal default, in case
RSTCONF is negated during HRESET asserted or taken from the Flash
1
/E
2
PROM/BCSR (MS 8
bits of the data bus) in case RSTCONF signal is asserted along with HRESET. The default
configuration word can be taken from the E
2
PROM/BCSR in case the Flash has been tampered
with. The selection between the BCSR, FLASH and the E
2
PROM as the source of the default
configuration word is determined by a dedicated dip-switch (see
Section 2.3.5
) and a jumper (see
Section 2.3.4
).
During hard reset sequence, the configuration master
2
reads the Flash (or E
2
PROM or BCSR)
memory at addresses 0, 8, 0x18, 0x20,... a byte each time, to assemble the 32 bit configuration
word. A total of 64 bytes of data is read from D(0:7) to acquire 8 full configuration words for
system that may have upto 8 PQ2 chips.
The configuration word for a single
3
PQ2 is stored in the Flash memory SIMM, in the E
2
PROM
or as default in the BCSR, while the other seven words are not initialized, as there are no
additional PQ2 on the PQ2FADS-VR. The default configuration word is shown in
Table 4-1.
for
the FLASH and in
Table 4-2.
for the E
2
PROM. PCI module configuration is 256 Bytes long and
should start at address 0x100.
There are four possible configuration words:
PQ2FADS-VR without L2 Cache - FLASH/BCSR is the boot device. CS0 is assigned to
the FLASH and CS4 is assigned to the E
2
PROM.
1. In general, from any device residing on CS0.
2. In general, The PQ2 for which RSTCONF is asserted along with PORST asserted or in particular, the
PQ2 residing on the PQ2FADS-VR.
3. Although the PQ2 as configuration master reads 8 configuration words, only the 1’st configuration word
is influential.
F
Freescale Semiconductor, Inc.
n
.
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