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參數(shù)資料
| 型號(hào)： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 37/186頁(yè) |
| 文件大?。?/td> | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
MOTOROLA
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
25
- after power-on reset
. If a hard reset sequence is entered later, MODCKH(0:3), although
sampled, are don’t care.
The PCI_MODCK signal, which is sampled concurrently with the PCI_MODCK(0:3) pins,
determines the PCI bus clock frequency (see
Section 2.3.7
). When set high, it divides the PCI bus
frequency by two. When reset low, the PCI bus frequency is as determined by the MODCK(1:3)
and PCI_MODCKH(0:3) signals.
4.1.2
Hard Reset
Hard-Reset may be generated on the ADS by the following sources:
1. COP/JTAG Port
2. Manual Hard reset.
3. PQ2’s internal sources.
Hard-Reset, when generated, causes the PQ2 to reset all its internal hardware except for PLL
logic, re-acquires the Hard-reset configuration from its current source, and jumps to the Reset
vector in the exception table. Since hard-reset resets also the refresh logic for dynamic RAMs,
their content is lost as well.
HRESET when asserted, is extended internally by the PQ2 for additional 512 bus clock cycles at
the end of which, the PQ2 waits for 16 bus clock cycles and then, re-checks the state of the
HRESET line.
HRESET is an open-drain signal and must be driven with an open-drain gate by which ever
external source is driving it. Otherwise, contention will occur over that line, which might cause
permanent damage to either board logic and/or to the PQ2 itself.
4.1.2.1 COP/JTAG Port Hard - Reset
To provide convenient hard-reset capability for a COP/JTAG controller, HRESET line appears at
the COP/JTAG port connector. The COP/JTAG controller may directly generate hard-reset by
asserting (low) this line.
4.1.2.2 Manual Hard Reset
To allow run-time Hard-reset, when the COP controller is disconnected from the PQ2FADS-VR
and to support resident debuggers, manual Hard is facilitated. Depressing both Soft-Reset (SW3)
and ABORT (SW2) buttons assert
s
the HRESET pin of the PQ2, generating a HARD RESET
sequence.
Since the HRESET line may be driven internally by the PQ2, it must be driven to the PQ2 with an
open-drain gate. If off-board H/W connected to the PQ2FADS-VR is to drive HRESET line, then
it should do so with an open-drain gate, this, to avoid contention over this line.
When Hard Reset is generated, the PQ2 is reset in a destructive manner, i.e., the hard reset
configuration is re-sampled and all registers (except for the PLL’s) are reset, including memory
controller registers - reset of which results in a loss of dynamic memory contents.
To save on board’s real-estate, this button is not a dedicated one, but is shared with the Soft-Reset
button and the ABORT button - when both are depressed, Hard Reset is generated.
F
Freescale Semiconductor, Inc.
n
.
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