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| 型號： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶手冊 |
| 文件頁數(shù)： | 50/186頁 |
| 文件大?。?/td> | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
38
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Cache is used, the Flash, EEPROM, BCSR and
PCI Interrupt Controller are not accesible. For
further details, consult the PQ2 User Manual.
4.5
Buffering
In order to achieve best performance, it is necessary to reduce the capacitive load over the 60X
bus as much as possible. Therefore, the slower devices on the bus, i.e., the Flash SIMM,
E
2
PROM, ATM UNI M/P interface, PCI Interrupt Controller and the BCSR are buffered, while
the SDRAM and the cache are not buffered from the 60X bus.
Latches are provided over address and strobe (when necessary) lines while transceivers are
provided for data. Use is done with 74ALVT buffers (by Philips) which are 3.3V operated and 5V
tolerant
1
and provide bus hold to reduce pull-up/pull-down resistors count (as required by the
PQ2). This type of buffers reduces noise on board due to reduced transitions’ amplitude.
To further reduce noise and reflections, serial damping resistors are placed over SDRAM address
and all PQ2 strobe lines.
The data transceivers are open only if there is an access to a valid
2
buffered board address or
during Hard - Reset configuration
3
. That way data conflicts are avoided in case an unbuffered
memory read or off-board memory is read - provided that it is not mapped to an address valid on
board. It is the users’ responsibility to avoid such errors.
4.6
Chip - Select Generator
The memory controller of the PQ2 is used as a chip-select generator to access on-board (and off-
board) memories, saving boards’ area, reducing cost, power consumption and increasing
flexibility. To enhance off-board application development, memory modules (including the
BCSRx) may be disabled via BCSR
4
in favor of an external memory connected via the expansion
connectors. That way, a CS line may be used off-board via the expansion connectors, while its
associated local memory is disabled.
When a CS region, assigned to a buffered
5
memory, is disabled via BCSR, the local data
transceivers are disabled during access to that region, avoiding possible
6
contention over data
lines.
1. Required for Flash, E
2
PROM, Interrupt Controller and BCSR
2. An address which is covered in a Chip-Select region, that controls a buffered device.
3. To allow a configuration word stored in the Flash/E
2
PROM memory to become active.
4. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply
power to the PQ2FADS-VR.
5. When an unbuffered CS region is being accessed, buffers do not open anyway.
6. During read cycles.
F
Freescale Semiconductor, Inc.
n
.
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| PQ2L3182MSPQ | 功能描述:低壓差穩(wěn)壓器 - LDO Dual 1.8V and 3.3V 250mA/ch RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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