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參數(shù)資料
| 型號(hào)： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 62/186頁(yè) |
| 文件大?。?/td> | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
50
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
clocks for each, hard-configured
1
.
The ATM SAR is connected to the physical medium by an optical interface. Use is done with
HP’s HFBR 5805 optical interface, which operates at 1300 nm with upto 2 Km transmission
range.
The ATM PHY is connected to IRQ7 and generates an interrupt when an appropriate event
occurs.
NOTE:
When the 60x Data Parity option is on, IRQ7 pin switches functionality to parity
and the interrupt output is routed to IRQ3. It is the responsibilty of the user to set
the appropriate functionality of the IRQ3 pin (SIUMCR register).
When 16 bit UTOPIA bus is used, the extra pins are in conflict with other
functions. In that case, the16 bit UTOPIA bus will disable the USB, RS232 port 2
and the Fast Ethernet MDC functions.
When Multi PHY UTOPIA bus is used, the extra pins are in conflict with other
functions. In that case, the multi PHY UTOPIA bus will disable the two RS232
port functions.
NOTE:
NOTE:
4.12.2 100/10 Base - T Ports
Two fast Ethernet ports with T.P. (100-Base-TX) I/F is provided on the PQ2FADS-VR. These
ports also support 10 Mbps ethernet (10-Base-T) via the same transceiver - the DM9161 by
Davicom.
The DM9161 are connected to FCC2 and FCC3 of the PQ2 via MII or RMII interface, which is
used for both - devices’ control and data path. The initial configuration of the DM9161 on the
PQ2FADS-VR is set by external resistors - 100Base-Tx Full Duplex in MII mode. The selection
between MII/RMII for FCC2 and FCC3 is done by jumpers JP2 and JP3 respectively. The
DM9161 must be set to MII or RMII while in power-down.
The DM9161 reset input is driven by either asserting the FETH_RST bit in BCSR1 (see
Table 4-
9.
) or by asserting a specific bit in an internal register via MII I/F.
To allow external use of FCC2 and FCC3, their pins appear at the CPM expansion connectors and
the ethernet transceiver may be Disabled / Enabled at any time via the MIIs’ MDIO port.
The DM9161 is able to interrupt the PQ2 via IRQ7 line. This line is shared also with the CPM
expansion connectors. Therefore, any tool that is connected to IRQ7, should drive these lines with
an Open Drain buffer.
NOTE:
When the 60x Data Parity option is on, IRQ7 pin switches functionality to parity
and the interrupt output is routed to IRQ3. It is the responsibilty of the user to set
the appropriate functionality of the IRQ3 pin (SIUMCR register).
4.12.2.1 DM9161 Control
The DM9161 is controlled via the MII management
2
port which is a 2 wire interface: a clock
1. Using resistors.
2. Also known as MII MDIO port.
F
Freescale Semiconductor, Inc.
n
.
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