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參數(shù)資料
| 型號(hào)： | PQ2FADSVRRM |
| 英文描述： | PQ2FADS-VR Users Manual |
| 中文描述： | PQ2FADS - VR的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 61/186頁(yè) |
| 文件大?。?/td> | 2001K |
| 代理商： | PQ2FADSVRRM |
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Functional Description
MOTOROLA
PQ2FADS-VR User’s Manual
For More Information On This Product,
Go to: www.freescale.com
49
4.12
Communication Ports
The PQ2FADS-VR has several communication ports, to allow convenient evaluation of the CPM
features. Obviously, it is not possible to provide all types of communication interfaces supported
by the CPM, but it is made convenient to connect any communication interface devices to the
PQ2 via the CPM Expansion connectors, residing on the edge of the board.
All CPM pins are visible on MICTOR connectors. In order to avoid long routes and stubs, bus
muxing devices are used to direct the CPM signals to a communication element on-board or to the
expansion connector. A signal that is used on-board, will not be visible in the expansion connector
and vise-versa. The control is done by enabling/disabling the communication elements on-board.
The communication ports’ interfaces provided on the PQ2FADS-VR are listed below:
1. 155 Mbps ATM UNI on FCC1 with Optical interface, using the UTOPIA Level 2 interface
- support for 8 or 16 bit in multi or single PHY.
2. Two 100/10-Base-T Ports on FCC2 and FCC3 with T.P. interface, MII or RMII (on Hip7
devices only) controlled.
3. Dual RS232 ports residing on SMC1 & SMC2.
4. USB port, 1.1 USB standard compliant, with speed control (12 or 1.5 Mbps) and mode
control (Host or slave).
4.12.1 ATM Port
To support the PQ2s’ ATM controller, a 155.52Mbps User Network Interface (UNI) is provided
on board, connected to FCC1 of the PQ2 via UTOPIA I/F. Use is done with PM5384 S/UNI-155-
ULTRA by PMC-SIERA. Although these transceivers are capable of supporting 51.84Mbps rate,
support is given to 155.52Mbps only. The PHY supports UTOPIA level 2 which means support
for 8 or 16 bit UTOPIA bus in single or multi PHY mode. The control over the mode of UTOPIA
bus connection is done through BCSR3.
The control over the transceiver is done using the microprocessor interface of the transceiver,
controlled by the PQ2 memory controllers’ GPCM. Since the UNI is 5V powered and the PQ2 is
3.3V powered (5V intolerant), the UNI is buffered (LCX buffers) from the PQ2 on both the
receive part of UTOPIA interface and the microprocessor control ports.
The ATM transceiver may be enabled / disabled at any time by writing ’0’ /’1’ respectively to the
ATMEN bit in BCSRx. When ATMEN is negated, (’1’) the microprocessor control port is also
detached from the PQ2 and its associated FCC may be used off-board via the expansion
connectors.
The ATM transceiver reset input is driven by HRESET signal of the PQ2, so that the UNI is reset
whenever a hard-reset sequence occurs. The UNI may also be reset by either asserting ATM_RST
bit in BCSR1 (see
Table 4-9.
) or by asserting (’1’) the RESET bit in the Master Reset and Identify
/ Load Meters register via the UNI microprocessor interface.
The UNI transmit and receive clocks are fed with a 19.44 MHz +/- 20 ppm, clock generator, 5 V
powered, while the receive and transmit fifos’ clocks of the UTOPIA interface are provided by
the PQ2. The PQ2 can provide the same clock for both UTOPIA transmit and receive or separate
F
Freescale Semiconductor, Inc.
n
.
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