參數(shù)資料
型號: PHASE
英文描述: Phase Lock Loop Configurations (1757k)
中文描述: 鎖相環(huán)配置(1757k)
文件頁數(shù): 9/20頁
文件大?。?/td> 1757K
代理商: PHASE
Revision 1.01/April 2002 Semtech Corp.
Page 9
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.3
Default Configuration for Independent T4 and T0 Paths
The default configuration for the ACS8530 for the T0 and T4 paths to produce simultaneous
independent clock outputs is shown in Figure 5.
This configuration will yield high jitter BITS/AMI clocks from the T4 path. In addition, the T4 APLL will yield
low jitter
OC-N clocks. The T0 path will yield low jitter OC-N, clocks and high jitter n x E1/DS1 simultaneously.
Figure 5
Default configuration of the T0 and T4 PLLs for simultaneous clock output.
The register settings for the default configuration are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = 1
Reg 35 bit 4 = 0
Reg 64 bit (2:0) = 001, see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = 00
Reg 65 bit (2:0) = 000, see Table 2
Must use
LOCK8K
相關(guān)PDF資料
PDF描述
PHASE-LOCKEDLOOP Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C
PHB11N03LT N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管)
PHD11N03LT N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管)
PHB129NQ04LT N-channel TrenchMOS logic level FET
PHP129NQ04LT N-channel TrenchMOS logic level FET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PHASE-2/VIEWCAST 制造商:Sliger Designs, Inc. 功能描述:3 CHASSIS THAT WILL BE FUNCTIONAL PROTOTYPES,LESS SWITCH OVE - Bulk
PHASE-3/VIEWCAST 制造商:Sliger Designs, Inc. 功能描述:3 CHASSIS THAT WILL BE ALPHA PRODUCTION UNITS SUITABLE FOR R - Bulk
PHASE3-KIT 制造商:FUJITSU 功能描述:EVALUATION KIT BOARD 1 FR MICRO
PHASE-LOCKEDLOOP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Controlled Ocillator
PHASFO 7.83/831/1 制造商:Vishay Intertechnologies 功能描述:HIGH VOLTAGE POWER CAPACITORS