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| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 13
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.7
T4 PLL Configured to Measure the Relative Phase Error between Inputs
The T4 DPLL PFD can be configured to measure the phase difference of the currently locked to input on
the T0 DPLL with respect to any other valid input.
The T4 DPLL PFD compares two inputs (usually the feedback and reference input) with each other and
performs some filtering. This filtering has a bandwidth of approx. 100 Hz. This will result in a digital
number representing the filtered phase difference between these two signals being available (normally
used for the digital synthesis).
The phase difference is reported in units of 0.707 degrees of the actual locking frequency. When direct
locking to high frequency input, the actual time is then scaled down and will give resolution down to e.g.
110 ps at 19.44 MHz in direct locking mode compared with 245 ns with Lock8K mode enabled with the
same 19.44 MHz input. The two inputs to the PFD have to be very close in frequency to give an accurate
phase measurement.
The phase difference measurement is held in the 16 bit register,
sts_current_phase
. The register is
updated on a 204.8 MHz cycle.
Under normal circumstances the frequency of the inputs to the PFD are determined by the input
frequency selection and the pre-divider mode settings such as Lock8K and DivN. The appropriate
feedback frequency is automatically selected from the supported spot frequencies to match the input
reference frequency (post division if necessary).
The feature to use the T4 PFD to measure the relative phase error between the selected T0 input and
the selected T4 input will require the user to ensure that the settings and frequency are the same for the
two inputs to be measured. Enabling the feature simply replaces the T4 DPLL feedback signal to the T4
PFD with the T0 PFD input reference signal. Reading the current phase register from the T4 path will yield
the filtered phase difference between the two inputs. If there is jitter or wander present on either or both
inputs, then this will have an effect on the measured phase. The extent of this effect will depend on the
frequency of the jitter/wander compared to the 100 Hz bandwidth of the filter.
The T4 PFD configuration is shown in Figure 9.
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