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參數(shù)資料
| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 14
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
Figure 9
T4 PFD configured to perform Phase Offset Measurement between selected T0 input and a
standby.
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = x
Reg 35 bit 4 = x
Reg 64 bit (2:0) = xxx
Reg 65 bit 7 = 1
Reg 65 bit 6 = 1 (if required)
Reg 65 bit (5:4) = 12 E1 (00), 16 E1 (01), 16 DS1 (11) or 24 DS1 (10) - see Table 1
Reg 65 bit (2:0) = 000
path6
Select stand-by source
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| PHASE-LOCKEDLOOP | Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PHASE-2/VIEWCAST | 制造商:Sliger Designs, Inc. 功能描述:3 CHASSIS THAT WILL BE FUNCTIONAL PROTOTYPES,LESS SWITCH OVE - Bulk |
| PHASE-3/VIEWCAST | 制造商:Sliger Designs, Inc. 功能描述:3 CHASSIS THAT WILL BE ALPHA PRODUCTION UNITS SUITABLE FOR R - Bulk |
| PHASE3-KIT | 制造商:FUJITSU 功能描述:EVALUATION KIT BOARD 1 FR MICRO |
| PHASE-LOCKEDLOOP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Controlled Ocillator |
| PHASFO 7.83/831/1 | 制造商:Vishay Intertechnologies 功能描述:HIGH VOLTAGE POWER CAPACITORS |
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