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參數資料
| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數： | 2/20頁 |
| 文件大小： | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 2
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
Table of Contents
List of Sections
Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 T0 DPLL Architecture and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 T4 DPLL Architecture and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3 Default Configuration for Independent T4 and T0 Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 Alternative Configuration for Independent T0 and T4 Paths . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Configuration for Low Jitter E3/DS3 and OC-N Clock Generation with No Independent T4
Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6 Configuration for Low Jitter E3/DS3 and E1/DS1 with No Independent T4 Path . . . . . . . . . .12
2.7 T4 PLL Configured to Measure the Relative Phase Error between Inputs . . . . . . . . . . . . . . . .13
2.7.1
Examples of T4 PFD used for Phase Measurement . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8 T4 Low Frequency Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Appendix 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
ACS8530 PLL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Basic T0 configuration for OC-N and n x E1/DS1 outputs (low and high jitter).. . . . . . . . . . . .6
Basic T4 configuration for independent BITS/SSU output. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
T4 configuration for low jitter independent BITS/SSU and OC-N clock outputs. . . . . . . . . . . .8
Default configuration of the T0 and T4 PLLs for simultaneous clock output.. . . . . . . . . . . . . .9
Alternative configuration for independent T0 and T4 outputs. . . . . . . . . . . . . . . . . . . . . . . . .10
Configuration for low jitter E3/DS3 and OC-N clock generation with no independent T4
path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Configuration for low jitter E3/DS3 and E1/DS1 with no independent T4 path. . . . . . . . . . .12
T4 PFD configured to perform Phase Offset Measurement between selected T0 input and a
standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 8
Figure 9
List of Tables
Table 1
Table 2
Table 3
Phase measurement examples using T4 PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
T0 DPLL Frequency Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
T4 DPLL Frequency Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
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