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| 型號(hào)： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
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Revision 1.01/April 2002 Semtech Corp.
Page 10
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.4
Alternative Configuration for Independent T0 and T4 Paths
An alternative configuration for the ACS8530 for independent T0 and T4 paths to produce simultaneous
clock outputs is shown in Figure 6.
This configuration will yield high jitter BITS/AMI outputs from the T4 path. The T0 path will yield low jitter
OC-N and high jitter n x E1/DS1 plus a low jitter version of the n x E1/DS1 from the T4 APLL.
Figure 6
Alternative configuration for independent T0 and T4 outputs.
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = 1
Reg 35 bit 4 = 0
Reg 64 bit (2:0) = 12 E1 (010), 16 E1 (011), 16 DS1 (101) or 24 DS1 (100), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 1
Reg 65 bit (5:4) = 12 E1 (00), 16 E1 (01), 16 DS1 (11) or 24 DS1 (10), see Table 2
Reg 65 bit (2:0) = 000
path2
Configure for 16E1 or 16DS1 mode for lower jitter BITS/AMI
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