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| 型號(hào)： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 12
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.6
Configuration for Low Jitter E3/DS3 and E1/DS1 with No Independent T4 Path
The configuration for the ACS8530 where the T0 and T4 paths are locked to the T0 is shown in Figure 8.
This configuration will yield low jitter E3/DS3 outputs from the T4 path. The T0 path will yield low jitter
n x E1/DS1.
Figure 8
Configuration for low jitter E3/DS3 and E1/DS1 with no independent T4 path.
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 1
Reg 35 bit 6 = 0
Reg 35 bit 4 = x
Reg 64 bit (2:0) = E3 (110) or DS3 (111), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = xx
Reg 65 bit (2:0) = 12 E1 (010), 16 E1 (011), 16 DS1 (101) or 24 DS1 (100), see Table 2
path 5
Configure for E3/DS3 mode as required
Note... Digital feedback is required to match digital output,
for synchronization reasons
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