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| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 11
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.5
Independent T4 Path
Configuration for Low Jitter E3/DS3 and OC-N Clock Generation with No
The configuration for the ACS8530 for E3/DS3 generation, where the T0 and T4 paths are locked to the
T0, is shown in Figure 7.
This configuration will yield low jitter E3/DS3 outputs from the T4 path. The T0 path will yield low jitter
OC-N and high jitter n x E1/DS1.
Figure 7
Configuration for low jitter E3/DS3 and OC-N clock generation with no independent T4 path.
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 1
Reg 35 bit 6 = 0
Reg 35 bit 4 = x
Reg 64 bit (2:0) = E3 (110) or DS3 (111), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = xx
Reg 65 bit (2:0) = 000, see Table 2
path4
Configure for E3/DS3 mode as required
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