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| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 18
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
Bit 3
Not used
Bits [2:0]
T0_DPLL_frequency
Register to configure the frequency of operation of the DPLL/APLL in the T0 path. This register
affects the frequencies available at outputs TO1 - TO7, see Reg. 60 - Reg. 63.
000
77.76 MHz, digital feedback, T0 APLL frequency = 311.04 MHz.
001
77.76 MHz, analog feedback, T0 APLL frequency = 311.04 MHz.
010
12E1, T0 APLL frequency = 98.304 MHz.
011
16E1, T0 APLL frequency = 131.072 MHz.
100
24DS1, T0 APLL frequency = 148.224 MHz.
101
16DS1, T0 APLL frequency = 98.816 MHz.
110
Not used.
111
Not used.
Table 2 T0 DPLL Frequency Configurations
Mode
Frequencies available for selection at the outputs TO1-TO7 (MHz)
T0 DPLL
OC-N
311.04
155.52
77.76
51.84
38.88
25.92
19.44
6.48
12E1
98.304
49.152
24.576
16.384
12.288
8.192
6.144
2.048
16E1
131.072
65.536
32.768
21.84533
16.384
10.922667
8.192
2.7306667
24DS1
148.224
74.112
37.056
24.704
18.528
12.352
9.264
3.088
16DS1
98.816
49.408
24.704
16.46933
12.352
8.2346667
6.176
2.0586667
Table 3 T4 DPLL Frequency Configurations
T4 DPLL Mode
Frequencies available for selection at the outputs TO1-TO7(MHz)
OC-N
155.52
77.76
38.88
19.44
6.48
4.86
12E1
49.152
24.576
12.288
6.144
2.048
1.536
16E1
65.536
32.768
16.384
8.192
2.7306667
2.048
24DS1
74.112
37.056
18.528
9.264
3.088
2.316
16DS1
49.408
24.704
12.352
6.176
2.0586667
1.544
E3
137.472
68.736
34.368
17.184
5.728
4.296
DS3
89.472
44.736
22.368
11.184
3.728
2.796
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