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參數(shù)資料
| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 15
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.7.1
Examples of T4 PFD used for Phase Measurement
Table 1 gives examples of possible outcomes when T4 PFD used to measure phase between two valid
input reference sources, where the ACS8530 has following valid inputs:
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
inactive
inactive
19.44 MHz, direct locking
19.44 MHz, direct locking
77.76 MHz, Lock8K enabled
77.76 MHz, Lock8K enabled
2.048 MHz, direct locking
2.048 MHz, direct locking
10 MHz, DivN to 8 kHz enabled
10 MHz, DivN to 8 kHz enabled
inactive
inactive
inactive
inactive
2.8
T4 Low Frequency Outputs
The TO8 output is an AMI composite clock output. This always produces a 64 kHz/8 kHz composite
clock. TO9 always produces an E1/DS1 frequency output for a BITS/SSU application. Both TO8 and TO9
are generated by DFS within either the T0 or T4 path, as controlled by Register 35 Bit 4. The frequencies
generated from TO8 and TO9 are independent of the mode (frequency) of either the T4 or the T0 paths.
The amount of jitter generated on the TO8 and TO9 outputs will be related to the clock period of the
source DFS block added to any jitter present on that clock. This is detailed in the following text. As can
be seen in the block diagram in Figure 1, the DFS blocks used to generate these outputs are the T4
feedback DFS block in the case of the T4 path and the T0 LF output DFS block for the T0 path. The T4
feedback DFS block is clocked by the T4 forward DFS, or its APLL. The frequency of the T4 forward DFS
block can be determined by referring to the ACS8530 data sheet, Table 13 (T4 APLL frequencies). This
is in the region of 65 MHz to 89 MHz and can be approximated to have a period of between 11 ns and
15 ns. The output of the T4 forward DFS block will have an inherent pk-pk jitter of approximately 4.9 ns.
Table 1 Phase measurement examples using T4 PFD
Example
T0 Path Input Selection
T4 Input Selection
Result/Problems
Case 1
I3
I4
Meaningful result
Any other input
Result not meaningful
Case 2
I5
I6
Can measure result, but phase error in 245 ns resolution
due to locking at 8 kHz (period of 77.76 MHz is 13 ns)
Any other input
Result not meaningful
Case 3
I3
I8
Meaningful result
Any other input
Result not meaningful
Case 4
I3
I10
Can measure result, but phase error in 245 ns resolution
due to locking at 8 kHz (period of 10 MHz is 100 ns)
Any other input
Result not meaningful
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