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參數(shù)資料
| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 6
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
DFS block, the input to that block comes directly from the T0 77.76 MHz output DFS block so that a
"loop" is not created.
The T0 output APLL is for multiplying and filtering. The input to the T0 output APLL can be either
77.76 MHz from the T0 77.7 6MHz output DFS block or an alternative frequency from the T0 LF output
DFS block (offering 77.76 MHz, 12 x E1, 16 x E1, 16 x DS1 or 24 x DS1). The frequency from the T0
output APLL is 4 times it's input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. The T0
output APLL is subsequently divided by 1, 2, 4, 6, 8, 12, 16 or 48, and these are available at the TO1-
TO7 outputs.
Figure 2
Basic T0 configuration for OC-N and n x E1/DS1 outputs (low and high jitter).
2.2
T4 DPLL Architecture and Features
The main features of the T4 DPLL are:
z
Programmable DPLL bandwidth in 3 steps from 18, 35 and 70 Hz.
z
Programmable damping factor: For optional faster locking and peaking control. Factors = 1.2, 2.5, 5,
10 or 20.
z
Multiple phase lock detectors.
z
Multi-cycle phase detection and locking, programmable up to +/-8192 UI - improves jitter tolerance
in direct lock mode.
z
N x E1/DS1 including 12 x E1, 16 x E1, 16 x DS1 and 24 x DS1 supported.
z
E3/DS3 (44.736 MHz/34.368 MHz) support.
z
Low jitter N x E1/DS1 options.
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
z
Can use the T4 DPLL as an Independent FrSync DPLL.
path 7
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