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| 型號(hào)： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 8
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
Figure 4
T4 configuration for low jitter independent BITS/SSU and OC-N clock outputs.
The input to the T4 output APLL can be programmed to be one of the following:
z
Output from the T4 forward DFS block
z
12 x E1 from T0
z
16 x E1 from T0
z
16 x DS1 from T0
z
24 x DS1 from T0
The T4 path can be operated at a number of frequencies. This is to enable the generation of extra output
frequencies, which cannot be easily related to 77.76 MHz. When the T4 path is selected to lock to the
T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL. This is because all of the frequencies of
operation of the T4 path can be divided to 8 kHz and this will ensure synchronization of all the
frequencies within the two paths.
The frequency generated from the T4 output APLL block is four times its input frequency i.e. 311.04 MHz
when used with a 77.76 MHz input. The T4 output APLL is subsequently divided by 2, 4, 8, 12, 16, 48
and 64 and these are available at the TO1-TO7 outputs.
The TO8 and TO9 outputs are driven from either the T4 or the T0 path.
The TO10 and TO11 outputs are always generated from the T0 path. Reg.7A Bit 7 selects whether the
source of the 2 kHz and 8 kHz outputs available from TO1-TO7 is derived from either the T0 or the T4
path1
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