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參數(shù)資料
| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 17
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
Register 64 -
cnfg_T4_PLL_Freq
Bits [2:0]
T4_DPLL_frequency
Register to configure the frequency of operation of the DPLL in the T4 path. The frequency of the
DPLL will also affect the frequency of the T4 APLL which, in turn, affects the frequencies
available at outputs TO1 - TO7. It is also possible to not use the T4 DPLL at all, but use the T4
APLL to run directly from the T0 DPLL output, see Register 65 (
cnfg_T0_DPLL_frequency
).
000
001
010
011
100
101
110
111
T4 DPLL squelched (clock off).
77.76 MHz (OC-N rates), T4 APLL frequency = 311.04 MHz.
12E1, T4 APLL frequency = 98.304 MHz.
16E1, T4 APLL frequency = 131.072 MHz.
24DS1, T4 APLL frequency = 148.224 MHz.
16DS1, T4 APLL frequency = 98.816 MHz.
E3, T4 APLL frequency = 274.944 MHz.
DS3, T4 APLL frequency = 178.944 MHz.
Register 65 - c
nfg_T0_DPLL_Frequency
Bit 7
T4_meas_T0_ph
Register bit to control the feature to use the T4 path to measure phase offset from the T0 path.
When enabled the T4 path is disabled and the phase detector is used to measure the phase
between the input to the T0 DPLL and the selected T4 input.
0
1
Normal - T4 Path normal operation.
T4 DPLL disabled, T4 phase detector used to measure phase between selected T0 input
and selectedT4 input.
Bit 6
T4_APLL_for_T0
Register bit to select whether the T4 APLL takes its input from the T4 DPLL or the T0 DPLL. If the
T0 DPLL is selected then the frequency is controlled by Bits [5:4],
T0_freq_to_T4_APLL
.
0
1
T4 APLL takes its input from the T4 DPLL.
T4 APLL takes its input from the T0 DPLL.
Bits [5:4]
T0_freq_to_T4_APLL
Register to select the T0 frequency driven to the T4 APLL when selected by Bit 6,
T4_APLL_for_T0
.
00
01
10
11
12E1, T4 APLL frequency = 98.304 MHz.
16E1, T4 APLL frequency = 131.072 MHz.
24DS1, T4 APLL frequency = 148.224 MHz.
16DS1, T4 APLL frequency = 98.816 MHz.
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