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| 型號(hào)： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 4
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
The DPLLs in the ACS8530 are uniquely very programmable for all PLL parameters of bandwidth (from
0.5 mHz up to 70 Hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0
to 80 ppm, typically 9.2 ppm), input frequency (12 common SONET/SDH spot frequencies) and input-to-
output phase offset (in 6 ps steps up to 200 ns).
There is no requirement to understand the loop filter equations or detailed gain parameters since all
high level factors such as overall bandwidth can be set directly via registers in the microprocessor
interface.
The T0 path DPLL by default always produces an output at 77.76 MHz to feed the APLL, regardless of
the frequency selected at the output pins. The T4 path can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz.
When the T4 path is selected to lock to the T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL.
This is because all of the frequencies of operation of the T4 path can be divided to 8 kHz and this will
ensure synchronization of all the frequencies within the two paths. Both the DPLL's outputs are
connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number
of frequencies simultaneously available for selection at the output clock ports. The various combinations
of DPLL, APLL and divider configurations allow for generation of a comprehensive set of frequencies, as
listed in ACS8530 datasheet. To synchronize the lower output frequencies when the T0 PLL is locked to
a high frequency reference input, an additional input is provided. The SYNC2K pin (pin 45) is used to
reset the dividers that generate the 2 kHz and 8 kHz outputs such that the output 2/8 kHz clocks are
precisely aligned with the input 2 kHz.
The T4 DPLL is similar in structure to the T0 DPLL, but since the T4 is only providing a clock synthesis
and input to output frequency translation function, with no defined requirement for jitter attenuation or
input phase jump absorption, then its bandwidth is limited to the high end and the T4 does not
incorporate any of the Phase Build-out and adjustment facilities of the T0 DPLL.
The T0 and T4 PLL paths support the following common features:
z
Automatic source selection according to input priorities and quality level.
z
Different quality levels (activity alarm thresholds) for each input.
z
Variable bandwidth, lock range and damping factor.
z
Direct PLL locking to common SONET/SDH input frequencies or any multiple of 8 kHz.
z
Automatic mode switching between Free run, Locked and Holdover states.
z
Fast detection on input failure and entry into Holdover mode (holds at the last good frequency
value).
z
Frequency translation between input and output rates via direct digital synthesis.
z
Multi-cycle phase detection and locking, programmable up to +/-8192 UI for improved jitter
tolerance in direct lock mode.
z
Multiple n x E1/DS1 outputs supported.
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