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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
17
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
If Caller ID is supported in the system, the designer can
enable the 303DL to pass this information to the SDO
output. Following the completion of the first ring, the
system should set the ONHM bit (register 5, bit 3). This
bit must be cleared at the conclusion of the receipt of the
caller ID data and prior to the next ring burst.
The PCT303D can support a wake-up-on-ring function
using the RGDT signal. Refer to “Power Management”
on page 22 for more details.
Improved JATE Support
The HYBD pin connects to a node on the internal hybrid
cancellation circuit providing a pin for balancing
capacitor C12. C13 adds the necessary transmit out-of-
band filtering required to meet JATE out-of-band noise
specifications. The addition of C13 alters the transmit
path frequency response which must be balanced with
capacitor C12 to obtain maximum hybrid cancellation.
Digital Interface
The 303DL has two serial interface modes that support
most standard modem DSPs. The M0 and M1 mode
pins select the interface mode. The key difference
between these two serial modes is the operation of the
FSYNC signal. Table 8 summarizes the serial mode
definitions.
The digital interface consists of a single, synchronous
serial link which communicates both telephony and
control data.
In serial mode 0 or 1, the PCT303D operates as a
master, where the master clock (MCLK) is an input, the
serial data clock (SCLK) is an output, and the frame
sync signal, (FSYNC) is an output. The MCLK frequency
and the value of the sample rate control registers 7, 8, 9
and 10 determine the sample rate (Fs). The serial port
clock, SCLK, runs at 256 bits per frame, where the frame
rate is equivalent to the sample rate. Refer to “Clock
Generation Subsystem” on page 19 for more details on
programming sample rates.
The 303DL transfers 16-bit or 15-bit telephony data in
the primary timeslot and 16-bit control data in the
secondary timeslot. Figure 8 and Figure 9 on page 18
show the relative timing of the serial frames. Primary
frames occur at the frame rate and are always present.
To minimize overhead in the external DSP, secondary
frames are present only when requested.
RNG1/
RNG2
RGDT
SDO
DIGITIZED LINE SIGNAL
Figure 7 Ring Detect Timing
0.5–1.5 Sec.
DATA
> 0.2 Sec.
First Ring
0.2–3.0 seconds
Table 8 Serial Modes
Mode
0
1
2
3
M1
0
0
1
1
M0
0
1
0
1
Description
FSYNC frames data
FSYNC pulse starts data frame
Slave mode
Reserved
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