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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
23
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
The on-hook line monitor can also be used to detect
whether a phone line is physically connected to the
PCT303L and associated circuitry. When the on-hook
line monitor is activated (if no line is connected), the
output of SDO moves towards a negative full scale value
(–32768). The value is guaranteed to be at least 89% of
negative full scale.
If a line is present while in on-hook line monitor mode,
SDO has a near zero value. The designer must allow for
the group delay of the receive filter (5/Fs) before making
a decision.
Loop Current Monitor
When the system is in an off-hook state, the LCS bits of
register 12 indicate the approximate amount of DC loop
current that is flowing in the loop. The LCS is a 4-bit
value ranging from zero to fifteen. Each unit represents
approximately 6 mA of loop current from LCS codes
1-14. The typical LCS transfer function is shown in
Figure 13.
Figure 13 Typical LCS Transfer Function
An LCS value of zero means the loop current is less than
required for normal operation and the system should be
on-hook. Typically, an LCS value of 15 means the loop
current is greater than 140 mA.
The LCS detector has a built-in hysteresis of 2 mA of
current. This allows for a stable LCS value when the
loop current is near a transition level. The LCS value is
a rough approximation of the loop current, and the
designer is advised to use this value in a relative means
rather than an absolute value.
This feature enables the modem to determine if an
additional line has “picked up” while the modem is
transferring information. In the case of a second phone
going off-hook, the loop current falls approximately 50%
and is reflected in the value of the LCS bits.
Multiple Device Support
The 303DL supports the operation of up to 7 additional
devices on a single serial interface. Figure 17 on page
27 shows the typical connection of the 303DL and one
additional serial CODEC.
The 303DL must be the master in this configuration. The
secondary CODEC should be configured as a slave
device with SCLK and FSYNC as inputs. On power up,
the 303DL master is unaware of the additional CODEC
on the serial bus. The FC/RGDT pin is an input,
operating as the hardware control for secondary frames.
The RGDT/FSD pin is an output, operating as the active
low ring detection signal. It is recommended that the
master device be programmed for master/slave mode
prior to enabling the ISOcap, because a ring signal
causes a false transition to the slave device’s FSYNC.
Register 14 provides the necessary control bits to
configure the 303DL for master/slave operation. Bit 0
(DCE) sets the 303DL in master/slave mode, also
referred to as daisy-chain mode. When the DCE bit is
set, the FC/RGDT pin becomes the ring detect output
and the RGDT/FSD pin becomes the delay frame sync
output.
Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be
supported on the serial bus. For each slave, the 303DL
generates a FSYNC to the DSP. In daisy-chain mode,
the polarity of the ring signal can be controlled by bit 1
(RPOL). When RPOL = 1, the ring detect signal (now
output on the FC/RGDT pin) is active-high.
The
TLC320AC01 and the TLC320AD50 CODECs as well
as additional 303DLs. The type of slave CODEC(s) used
is set by bits 4:3 (SSEL1:SSEL0). These bits determine
the type of signalling used in the LSB of SDO. This
assists the DSP in isolating which data stream is the
master and which is the slave. If the LSB is used for
signalling, the master device has a unique setting
relative to the slave devices. The DSP can use this
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
303DL
supports
the
Texas
Instruments
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master 303DL generates
an FSYNC signal for each device every 16 or 32 SLCK
periods. The delay period is set by register 14, bit 2
(FSD). Figure 15 and Figure 16 on page 26 show the
relative timing for a single slave device. Note that
primary communication frames occur in sequence,
followed by secondary communication frames, if
requested.
15
0
0
5
10
6 12
66
60
54
48
42
36
30
24
18
72 78 84 90 96
140
LCS
BIT
Loop Current (mA)
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