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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
45
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL C
ONTROL
R
EGISTERS
!
PRELIMINARY
PRELIMINARY
DAA Control 2
(Register 6, R/W)
Reset settings: 70h
Bit Definitions:
PLL1 Divide N1
(Register 7, R/W)
Reset settings: 00h (serial mode 0, 1, 2)
Bit Definitions:
CPE
7
ATM1
6
ARM1
5
PDL
4
PDN
3
Reserved
2
ATM0
1
ARM0
0
Bits
Name
CPE
Description
Charge pump enable.
1 = Charge pump on (the V
A
pin should not be connected to a supply.
V
D
= 3.3 V ± 10%).
0 = Charge pump off.
AOUT transmit path level control.
7
6,1
ATM[1:0]
5,0
ARM[1:0]
AOUT receive path level control.
4
PDL
Power down line-side chip.
1 = Places the PCT303L in lower power mode.
0 = Normal operation. Program the clock generator before clearing this bit.
Power down. 1 = Powers down the 303DL. A reset pulse on RESET is required
to restore normal operation.
Reserved. Read returns zero.
3
PDN
2
Reserved
Divider N1
7
6
5
4
3
2
1
0
ATM[1:0]
00
01
10
11
Description
–20dB transmit path attenuation for call progress AOUT pin only.
–32dB transmit path attenuation for call progress AOUT pin only.
Mutes transmit path for call progress AOUT pin only.
–26dB transmit path attenuation for call progress AOUT pin only.
ARM[1:0]
00
01
10
11
Description
0dB receive path attenuation for call progress AOUT pin only.
–12dB receive path attenuation for call progress AOUT pin only.
Mutes receive path for call progress AOUT pin only.
–6dB receive path attenuation for call progress AOUT pin only.
Bits
Name
Divider N1
Description
Contains the (value – 1) for determining the output frequency on PLL1.
7:0
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