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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
47
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL C
ONTROL
R
EGISTERS
!
PRELIMINARY
PRELIMINARY
Line-Side Status
(Register 12, R/W)
Reset settings: N/A
Bit Definitions:
Transmit and Receive Gain
(Register 13, R/W)
Reset settings: 00h
Bit Definitions:
CLE
7
FDT
6
Reserved
LCS
5
4
3
2
1
0
Bits
Name
CLE
Description
Com link error.
1 = Indicates a communication problem between the PCT303D and the
PCT303L. When it goes high, it remains high until a logic 0 is written to it.
Frame detect. Read-only.
1 = Indicates ISOcap communication frame lock has been established.
0 = Indicates inter-chip communication has not established frame lock.
Reserved. Read returns zero.
Loop current sense. Read-only.
Four-bit value returning the loop current in 6mA increments.
0 = Loop current < 0.4mA typical. 1111 = Loop current > 140mA.
See “Loop Current Monitor” on page 23.
7
6
FDT
5:4
3:0
Reserved
LCS
Reserved
7
CBID
6
REVB
ARX
1
ATX
0
5
4
3
2
Bits
Name
Reserved
CBID
Description
Reserved. Read returns zero.
Chip B ID. Read-only.
1 = Indicates the line-side has international support.
0 = Indicates the line-side is domestic only.
Chip revision. Read-only.
Four-bit value indicating the revision of the PCT303L (line-side) silicon.
0100 = Revision D.
Receive gain.
a
1 = A +6dB gain is applied to the receive path.
0 = 0dB gain is applied.
Transmit gain.
a
1 = A –3dB gain (attenuation) is applied to the transmit path.
0 = 0dB gain is applied.
7
6
5:2
REVB
1
ARX
0
ATX
a.
This bit should be zero if using register 15 to control gain.
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