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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
24
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
If FSD is set for 16 SCLK periods between FSYNCs,
only serial mode 1 can be used. In addition, the slave
devices must delay the tri-state to active transition of
their SDO sufficiently from the rising edge of SCLK to
avoid bus contention.
The 303DL supports the operation of up to eight 303DL
devices on a single serial bus. The master 303DL must
be configured in serial mode 1. The slave(s) 303DL is
configured in serial mode 2. Figure 17 on page 27
shows a typical master/slave connection using three
303DL devices.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD becomes the delay frame sync output, and
FC/RGDT becomes the ring detection output. In
addition, the internal PLLs are fixed to a multiply by 20.
This provides the desired sample rate when the
master’s SCLK is provided to the slave’s MCLK. Note
that the SCLK of the slave is a no connect in this
configuration.
The delay between FSYNC input and delayed frame
sync output (RGDT/FSD) will be 16 SCLK periods. The
RGDT/FSD output has a waveform identical to the
FSYNC signal in serial mode 0. In addition, the LSB of
SDO is set to zero by default for all devices in serial
mode 2.
Gain Control
The 303DL supports multiple gain and attenuation
settings for the receive and transmit paths, respectively,
through register 13. When the ARX bit is set, 6 dB of
gain is applied to the receive path. When the ATX bit is
set, –3 dB of gain is applied to the transmit path.
Register 15 can be used to provide additional gain
control. For register 15 to have an effect on the receive
and transmit paths, the ATX and ARX bits of register 13
must be zero.
The receive path can support gains of 0, 3, 6, 9, and 12
dB. The gain is selected by bits 2:0 (ARX2:ARX0). The
receive path can also be muted by setting bit 3 (RXM).
The transmit path can support attenuations of 0, 3, 6, 9,
and 12 dB. The attenuation is selected by bits 6:4
(ATX2:ATX0). The transmit path can also be muted by
setting bit 7 (TXM).
Filter Selection
The 303DL supports additional filter selections for the
receive and transmit signals. The IIR bit of register 16,
when set, enables the IIR filters defined in Table 28 on
page 59. This filter provides a much lower, however
non-linear, group delay than the default FIR filters.
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