參數(shù)資料
型號(hào)： PCT1789N
英文描述： PCT303DL
中文描述： PCT303DL
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 632K
代理商： PCT1789N
PC-TEL, Inc.
22
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
Knowing the MCLK frequency and desired sample rate
the values for the M1, N1, M2, N2 registers can be
determined. When determining these values, remember
to consider the range for each register as well as the
minimum update rate for the first PLL.
The values determined for M1, N1, M2, and N2 must be
adjusted by minus one when determining the value
written to the respective registers. This is due to internal
logic, which adds one to the value stored in the register.
This addition allows the user to write a zero value in any
of the registers and the effective divide by is one. A
special case occurs when both M1 and N1 and/or M2
and N2 are programmed with a zero value. When Mx
and Nx are both zero, the corresponding PLLx is
bypassed. Note that if M2 and N2 are set to zero, the
ratio of 25/16 is eliminated and cannot be used in the
above equation. In this condition the CGM bit has no
effect.
Power Management
The 303DL supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full power down mode.
The power management modes are controlled by the
PDN and PDL bits of register 6.
On power up, or following a reset, the 303DL is in reset
operation. In this mode, the PDL bit is set, while the PDN
bit is cleared. The PCT303D is fully operational, except
for the ISOcap. No communication between the
PCT303D and PCT303L can occur during reset
operation. Note, any bits associated with the PCT303L
are not valid in this mode.
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared. The PCT303D is fully operational and the
ISOcap is communicating information between the
PCT303D and the PCT303L. Note that the clock
generator must be programmed to a valid sample rate
prior to entering this mode.
The 303DL supports a low-power sleep mode. This
mode supports the popular wake-up-on-ring feature of
many modems. The clock generator registers 7, 8, and
9 must be programmed with valid non-zero values prior
to enabling sleep mode. Then, the PDN bit must be set
and the PDL bit cleared. When the 303DL is in sleep
mode, the MCLK signal may be stopped or remain
active, but it must be active before waking up the 303DL.
The PCT303D is non-functional except for the ISOcap
and RGDT signal. To take the 303DL out of sleep mode,
pulse the reset pin (RESET) low.
In summary, the power down/up sequence for sleep
mode is as follows:
1. Registers 7, 8, and 9 must have valid non-zero
values.
2. Set the PDN bit (register 6, bit 3) and clear the PDL
bit (register 6, bit 4).
3. MCLK may stay active or stop.
4. Restore MCLK before initiating the power-up
sequence.
5. Reset the 303DL using RESET pin (after MCLK is
present).
6. Program registers to desired settings.
The 303DL also supports an additional power-down
mode. When both the PDN (register 6, bit 3) and PDL
(register 6, bit 4) are set, the chip-set enters a complete
power-down mode and draws negligible current. Set the
PDL bit either before setting the PDN bit or at the same
time. In this mode, the RGDT pin does not function.
Normal operation may be restored using the same
process for taking the chip-set out of sleep mode.
Analog Output
The 303DL supports an analog output (AOUT) for
driving the call progress speaker found with most of
today’s modems. AOUT is an analog signal that is
comprised of a mix of the transmit and receive signals.
The receive portion of this mixed signal has a 0 dB gain,
while the transmit signal has a gain of –20 dB.
The AOUT level can be adjusted via the ATM and ARM
bits in control register 6. The transmit portion of the
AOUT signal can be set to –20 dB, –26 dB, –32 dB, or
mute. The receive portion of the AOUT signal can be set
to 0 dB, –6 dB, –12 dB, or mute. Figure 3 on page 7
illustrates a recommended application circuit. Note that
in the configuration shown, the LM386 provides a gain
of 26 dB. Additional gain adjustments may be made by
varying the voltage divider created by R1 and R3 of
Figure 3.
On-Hook Line Monitor
The 303DL allows the user to detect line activity when
the device is in an on-hook state. When the system is
on-hook, the line data can be passed to the DSP across
the serial port while drawing a small amount of DC
current from the line. This feature is similar to the
passing of line information (such as Caller ID), while on-
hook, following a ring signal detection. To activate this
feature, set the ONHM bit in register 5.
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