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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
29
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
normal operation, the FDT bit can be checked before
reading any bits that indicate information about the line
side. If FDT is not set, the following bits related to the
line side are invalid—RDT, LCS, CBID, REVB; the
RGDT operation will also be non-functional.
Following power-up and reset, the FDT bit is not set
because the PDL bit (register 6 bit 4) defaults to 1. In this
state, the ISOcap is not operating and no information
about the line side can be determined. The user must
program the clock generator to a valid configuration for
the system and clear the PDL bit to activate the ISOcap.
While the PCT303D and PCT303L are establishing
communication, the 303DL will not generate FSYNC
signals. Establishing communication will take less than
10 ms. Therefore, if the controlling DSP serial interface
is interrupt driven, based on the FSYNC signal, the
controlling DSP does not require a special delay loop to
wait for this event to complete.
The FDT bit can also indicate if the line side executes an
off-hook request successfully. If the line side is not
connected to a phone line (that is, the user fails to
connect a phone line to the modem), the FDT bit
remains cleared. The controlling DSP must allow
sufficient time for the line side to execute the off-hook
request. The maximum time for FDT to be valid following
an off-hook request is 10 ms. At this time, the LCS bits
indicate the amount of loop current flowing. For more
information, see “Loop Current Monitor” on page 23. If
the FDT bit fails to be set following an off-hook request,
the line-side chip must be reset. This is accomplished by
setting the PDL bit for at least 1 ms.
Another useful bit is the communication link error (CLE)
bit (register 12 bit 7). The CLE bit indicates a time-out
error for the ISOcap following a change to either PLL1
or PLL2. For more information, see “Clock Generation
Subsystem” on page 19. When the CLE bit is set, the
DSP side chip has failed to receive verification from the
line side that the clock change has been accepted in an
expected period of time (less than 10 ms). This
condition indicates a severe error in programming the
clock generator or possibly a defective line-side chip.
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